[time-nuts] Austron PRR-10 GPS discliplined Rb...

[Dr Bruce Griffiths]

Dr Bruce Griffiths wrote:
> David I. Emery wrote:
>   
>> On Sun, Jan 28, 2007 at 11:43:11AM +1300, Dr Bruce Griffiths wrote:
>>   
>>     
>>> The DDS will need to have an internal clock of at least 30MHz or so to 
>>> generate a usable 10MHz output.
>>>     
>>>       
>> 	Agreed, assuming the chip doesn't do clock multiplication as
>> several do...
>>
>>   
>>     
>>> Although theoretically it is possible to generate 10MHz from a DDS 
>>> clocked at 20MHz, in practice the necessary brick wall analog 
>>> reconstruction filter is unrealisable.
>>>     
>>>       
>> 	Given my option 1 (DDS clocked at 20 mhz) and NO clock multiplication
>> the phase comparison with the input could easily be at say 5 mhz or 1 mhz
>> without degrading anything very much I shouldn't think.   Should be obvious
>> on a scope doing the reverse engineering of course...
>>
>> 	Of course for phase comparison with the input, one actually does not
>> need much filtering as one is only using the NCO digital output as an input
>> to a phase comparator... spurs and so forth don't count at all here as they
>> get filtered out in the subsequent loop filter for the PLL (which is very
>> narrow).
>>
>>
>>   
>>     
> David
>
> I presume that the leading edge of the GPS receiver PPS pulse samples 
> the DDS phase accumulator register content.
> This is not possible with most modern DDS chips with integrated DACs, in 
> which the DDS accumulator or its truncated phase output is not 
> externally accessible, it cannot be read, nor is there any provision for 
> capturing the phase at the leading edge of an external signal.
>
> However one could always use a gate array to implement the digital part 
> of a DDS and include a phase capture register.
> An external DAC (and sine table) would be required to synthesize the 
> corrected sine wave frequency source output.
>
> Bruce
>
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>   
ADDENDUM

When sampling the phase accumulator of an NCO with the leading edge of 
an external signal, first the external signal must be synchronised to 
the NCO clock using a multistage synchroniser. The synchroniser output 
has an inherent timing jitter of about 2 clock cycles peak to peak which 
limits the sampled phase effective resolution. To increase the single 
shot sampled phase effective resolution, either the NCO clock frequency 
can be increased, incurring greater power dissipation and cost, or a TDC 
can be used to measure the synchroniser input output delay and combined 
with the sampled phase to increase the effective single shot sampled 
phase resolution without increasing the NCO clock frequency.

Bruce


Bruce