[time-nuts] Frequency divider design critique request

[Magnus Danielson]

From: "David C. Partridge" <david.partridge at dsl.pipex.com>
Subject: Re: [time-nuts] Frequency divider design critique request
Date: Fri, 11 Jul 2008 18:41:52 +0100
Message-ID: <F0D1B0221FB64FE68A2D10B20E996044 at APOLLO>

Hej David,

> Magnus Danielson:
> 
> 1) Please could you clarify what you're proposing with the series resistors?
> I get the idea about 10nF in parallel with R24-R26, though I'm not sure what
> the benefit is?   Those MUX control pins are going to sit pretty hard on 5V
> or pulled down to ground.

OK. I was thinking EMC here. You may think that this is a DC part of the design
but infact you have "DC-signals" hitting a board with sharp edges, so you could
very well have transmitter antennas here. Also, the succeptability of those
inputs to E or H field disturbance will affect the output of the mux, so
attempting to reduce the efficiency as E and H field antenna should be a
benefit for the stability. Bypassing the input connection from the push-
button to ground with caps just where deas leads hit the board will make the
E-field susceptability low, but the low loop area over to the resistors and
chip will also make the H-field susceptability low. Trying to analyze such a
problem would take either a good feeling about things, luck or experience to
quickly pinpoint. It is cheap enought to reduce the problem, even if I don't
think the risk is imminent.

Do you follow my lines of thought?

> 2) You said: 
> 
> >I am sure we can come up with some arrangement for that. Several handy
> time-nuts around.
> 
> Are you suggesting that I get more than one PCB made up, or that I get 1
> prototype made up and built to confirm it works mostly as I expect, and then
> get a batch made up for the group to play with?
> 
> Obviously if there's enough interest I could get a batch made, but it's a
> bit of a risk if I find problems when I build the first one!

Why not? It basically solves a problem most of us has, and only a few tweaks
away and it solves it fairly generically. The only think it doesn't do well is
handling 5 MHz souces rather than 10 MHz. Having that would solve many
problems. While not achieving full metrological levels of stability, I am sure
it could be handy for several time-nuts never the less. Only a few need that
upper level anyway. A good prooven design for enought stability and decent
money might be right. I would certainly not mind having a pair of those lying
around and I am sure I could put a few into continous use. Now that is my lab
alone...

> Extra features - well I guess I could have added a distribution amplifier as
> well, but I think that's a different project.  1pps isn't needed as the TB
> already provides that.

My point was that it was an output section away....

The PPS was since you do produce the signal and you can the same box to divide
down to PPS and say 1 kHz as being used by other designs. Think of a separate
10 MHz source... like a Rb or so. 1 kHz for the loop comparision and PPSes for
performance measurements.

> Synchronising with the TB 1ppS output - hey, come on, this is my first
> digital design project.   The impossible we do immediately, unfortunately
> miracles take a bit longer!  

Oh, I seem to expect alot. But really, the extra features was really thinking
out loud after asking the question "What would annoy me most when using such a
box that I only *almost* can do?".

If using counters with loadable initial state, setting it up to come out
correctly at synchronisation is not that hard.

> All,
> 
> CPLD - wassat?  OK, OK I have some idea, but that's about all I know.
> Anyway these are probably BGA stuff which I couldn't hope to hand solder
> anyway - it's enough of a stretch for me to think of hand soldering this SMT
> board.

With CPLD you don't need to do BGA. One form of FlatPACK as I recall it.
Not too hard to solder. Look at the lower end from Xilinx for instance...

I agree with Bruce that resynchroniserz would be expected. The TTL/CMOS you
have is however more stable in availability, but so far this has not been much
of a problem with CPLDs that I have tracked.

Cheers,
Magnus