[time-nuts] Tight PLL Tester
WarrenS
warrensjmail-one at yahoo.com
Thu Feb 11 11:19:57 UTC 2010
Bruce
Thanks for your response, as always you've give me plenty to think about.
>Bruce said: It is essential to understand exactly how this system works in
>theory.
Turns out to be too true.
After re-reading your last post several times,
I now finally understand what you are saying and why you are saying it.
It is because YOU do not yet understand how this method works.
I find that so unbelievable, that I had not considered that possibility.
Starting at the following line and pretty much everything after that,
although accurate statements,
THEY DO NOT APPLY to this method.
>To recover the phase fluctuations the EFC voltage has to be integrated.
...
ws
***************
----- Original Message -----
From: "Bruce Griffiths" <bruce.griffiths at xtra.co.nz>
To: "Discussion of precise time and frequency measurement"
<time-nuts at febo.com>
Sent: Wednesday, February 10, 2010 2:32 PM
Subject: Re: [time-nuts] Tight PLL Tester
> It is essential to understand exactly how this system works in theory.
> No amount of hand waving or protestations will make its problems go away
> if you use inappropriate signal processing methods.
>
> The tight PLL (or any other PLL) forces the VCO (VCOXO int this case) to
> servo the fluctuations in the phase difference between the test oscillator
> and the VCO to zero within the PLL bandwidth.
>
> To recover the phase fluctuations (assuming linearity of the VCO response
> to its voltage control input) the EFC voltage has to be integrated.
> Leaving aside the problems of saturation with most (but not all)
> integrators, the phase fluctuations at the output of the VCO can be
> recovered (to within a scale factor) by sampling the integrator output to
> produce a set of synthesized phase samples. Alternatively one can
> calculate the first differences of the periodic sequence of phase samples
> to produce a series of scaled frequency averages.
>
> In practice integrator saturation can be avoided by one of the following
> methods:
>
> 1) Using a precision voltage to frequency converter and a counter to form
> the integrator.
> This is how NIST used to do it.
> The VFC110 from TI appears suitable.
> Avoid using a synchronous VFC (eg AD652) as they suffer from injection
> locking effects:
> http://www.analog.com/static/imported-files/tutorials/MT-028.pdf
> However if one samples the VFC integrator output at the end of each
> integration the effect of injection locking can be corrected for.
> DVMs like the HP/Agilent 34401A use a variation of this technique.
> Another thing to be aware of is that a DVM may have a built in RC low pass
> filter between its input terminals and its ADC.
> The effect of this may be significant if the averaging time (integration
> period) is too short.
>
> 2) Use an integrating DVM to sample the EFC voltage.
> The DVM samples are equivalent (to within a scale factor) to a set of
> frequency average samples.
> However most (but not all) DVMs have a finite deadtime between successive
> integrations, where the internal integrator is rundown for example.
> If one uses an integrating DVM with finite deadtime then the calculated
> values of ADEV should be corrected using the bias functions tabulated in
> NBS special publication 140 and elsewhere:
> http://digicoll.manoa.hawaii.edu/techreports/PDF/NBS140.pdf
>
> 3) The PLL has a finite bandwidth so one can sample it at a sufficiently
> high rate (> 2X PLL bandwidth as the PLL isnt a brickwall filter) and
> calculate the required frequency averages from the sampled data. Unless a
> very high oversampling rate is used merely averaging the values of a fixed
> number of samples will be insufficiently accurate. Attempts to use an
> arbitrary low pass filter to average the samples will bias the results.
> The averaging filter must have a frequency response that is very close to
> the sinc response of an integrator with an integration period equal to the
> sample interval.
> However this method is the most expensive as a high resolution ADC capable
> of relatively high sampling rates (10x the PLL bandwidth??) is required.
>
> It is also essential to have sufficient isolation between the unit under
> test and the VCO to avoid significant mutual injection locking effects.
> To a first approximation such injection locking affects the PLL parameters
> so that the PLL loop parameters need to be measured whilst the PLL is
> closed when isolation is insufficient.
>
> If one uses one of the Minicircuits phase detectors rather than an
> arbitrary mixer then the isolation between the phase detector inputs is
> much higher (at low frequencies at least) than that for most mixers.
> Depending on the reverse isolation of the output buffers of the
> oscillators being compared this isolation may be sufficient to avoid an
> appreciable change in the PLL parameters. If the isolation is insufficient
> one then needs to use a suitable isolation amplifier between the the
> output of each oscillator and the phase detector.
> The phase noise of the isolation amplifier should be lower than that of
> the reference VCO (VCOCXO in this case).
> Suitable isolation amplifiers are readily available as are circuit
> schematics for isolation amplifiers known to have low phase noise you can
> build for youself.
> Just building an isolation amplifier using fast opamps or cascaded MMICs
> without verifying the resultant phase noise is counterproductive.
>
> Bruce
>
> WarrenS wrote:
>>
>> If there are any Nuts out there interested in helping to make available
>> to other Freq-Nuts a SIMPLE tester that I have found to be a VERY useful
>> low cost tool, contact me off line.
>> warrensjmail-one at yahoo.com
>>
>> The tool is based on an OLD but seldom used method called the "Tight
>> Phase-Lock Loop Method of measuring Freq stability".
>> For a block diagram and short description see Figure 1.7 at
>> http://tf.nist.gov/phase/Properties/one.htm#oneone
>>
>> What I have made for my own use is a bread board of a simple analog
>> version of the NIST's block diagram.
>> There are of course many different ways to actually build it, depending
>> on ones preferences, skills, and junk box.
>> It can be done using a DVM, or a high or low resolution ADC, or a freq
>> counter, or counter IC chips, a Pic or any simple micro, or a sound
>> card, Or many other ways.
>> The nice thing about the method is that it takes no expensive or critical
>> parts to get performance as good as most anything out there.
>> Its main performance limitation is ONLY the single EFC OSC used as the
>> reference.
>>
>>
>> My unit works 'Good enough' to be able to test many of the things that
>> Freq nuts are concerned with.
>> Basically it is nothing more than a high speed freq difference detector
>> that can detect VERY small freq changes in a very short time.
>> What one then does with that data is where the flexibility comes from.
>> I've used mine for AVARs plots, detecting very small freq modulation due
>> to PS noise, freq offset plots, setting an osc on freq in seconds instead
>> of what can take hours, GPSDO Noise and TC test, etc. etc. The list is
>> almost endless.
>>
>>
>> Some advantages of a tight PLL method are:
>> 1) It is very simple, cheap and easy to build, and small
>>
>> 2) Works well for comparing an Oscillators Freq offset, Freq Noise, Freq
>> modulation, over short time intervals
>>
>> 3) It provides very good sub pico Second Phase resolution even with
>> simple setups.
>>
>> 4) Its noise floor is low enough so that its limitation is the Reference
>> Osc.
>>
>> 5) The NIST says it can be used to one part in 1e14. I'm getting better
>> than 1e12 from it, limited by the HP10811 Ref Osc I use.
>>
>> 6) Would be easy to make into a PC board project for Time nuts that don't
>> access to all the high end equipment.
>>
>> 7) I have a working breadboard that I built from just my junk box parts
>> that has worked great for me for several different things
>>
>> Some of its disadvantages:
>> 1) It is not the best way to take long term phase drift differences,
>> where a simple phase difference device will work great.
>>
>> 2) It is not a DMDT and is not as flexible in many ways, but can be just
>> as accurate and a lot easier to build and less to go wrong and a whole
>> lot cheaper.
>>
>> 3) It is basically an analog device and does not have digital accuracy.
>> But for small freq differences, it is more than accurate enough to
>> provide great results.
>>
>> 4) For those luckily enough to already have a TSC5120A or better, you
>> don't need one, That is unless you want to verify its performance at
>> short Tau.
>>
>> 5) And maybe the biggest disadvantage is that many of the leading Freq
>> nuts on this site don't like it and seem to believe that it should not
>> work.
>> But maybe that is just because they don't have one and have not even
>> tested one and seem unwilling to give it any consideration.
>>
>> 6) A search of past post on the subject will show that many do not all
>> agree that this is a good idea,
>> but they don't have a working unit like I do, and I don't have the
>> expensive high end equipment that they have.
>>
>> ws
>>
>> PS
>> Sorry for the long post.
>> This is the best I can do to respond to the off line request I received
>> to find a way to make this subject more useful, constructive, cooperative
>> and less confrontational, and do it with less words and give more
>> details.
>> I am not looking for a list of all the possible ways that it can be done
>> wrong,
>> Or guesses on why it should not work as good as it does.
>> I'll leave that for others to discuss.
>> But if what they say does not agree with my experimental results, you can
>> bet I'll still comment on it Again.
>> *************
>>
>>
>>
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>
>
>
>
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