[time-nuts] Digital tight PLL method
Ulrich Bangert
df6jb at ulrich-bangert.de
Wed May 26 11:06:35 UTC 2010
Bob,
sure! But I own this stuff not only for this purpose...
Best regards
Ulrich Bangert
> -----Ursprungliche Nachricht-----
> Von: time-nuts-bounces at febo.com
> [mailto:time-nuts-bounces at febo.com] Im Auftrag von Bob Camp
> Gesendet: Mittwoch, 26. Mai 2010 12:57
> An: Discussion of precise time and frequency measurement
> Betreff: Re: [time-nuts] Digital tight PLL method
>
>
> Hi
>
> Sounds like your bill of material was a bit above $10.
>
> Bob
>
>
> On May 26, 2010, at 4:42 AM, Ulrich Bangert wrote:
>
> > Warren,
> >
> > you are not the only person to have ideas like this!
> >
> > I managed to get me a Stanford Research DS345 generator which gives
> > 1E-6 Hz frequency resolution for any frequency below 30 MHz (Can be
> > locked to any 10 MHz reference). At 10 MHz this resembles a
> relative
> > resolution of 1E-13. I used this generator in a digital pll
> where the
> > phase error was measured by a DBM and a a HP3457. The
> digital PLL was
> > a simple script written with my EZGPIB utility which controlled the
> > DS345 and read the HP3457 via IEEE488. The main difference to your
> > analogue solution is that it delivers a frequency measurement value
> > immediately (= the current setting of the DS345) without
> any knowledge
> > needed about the mixer's phase gain properties. And it is
> not limited
> > to a certain frequency. Of course, the generator may be
> exchanged by
> > an DIY DDS and the multimeter may be exchanged against a DIY A/D
> > converter. Injection locking is not a topic with the DDS circuit.
> >
> > Nevertheless my measurement were not exactly encouraging.
> May be that
> > I missed to apply the important math that Bruce has been
> suggesting in
> > the discussion with you. All the stuff is on my workbench
> and is ready
> > to use. May be I give it another try.
> >
> > Best regards
> > Ulrich Bangert
> >
> >> -----Ursprungliche Nachricht-----
> >> Von: time-nuts-bounces at febo.com
> >> [mailto:time-nuts-bounces at febo.com] Im Auftrag von WarrenS
> >> Gesendet: Montag, 24. Mai 2010 18:49
> >> An: John Miles; Tom Van Baak; Discussion of precise time and
> >> frequency measurement
> >> Betreff: [time-nuts] Digital tight PLL method
> >>
> >>
> >>
> >> Concerning the simple, $10, Low cost, Tight PLL method of
> doing ADEV.
> >>
> >> "If you accept that the measurement is going to be limited by
> >> the Reference
> >> Osc,
> >> Then for Low COST and SIMPLE, with the ability to measure
> >> ADEVs at very low
> >> levels,
> >> Can't beat a simple analog version of NIST's "Tight
> >> Phase-Lock Loop Method
> >> of measuring Freq stability".
> >> http://tf.nist.gov/phase/Properties/one.htm#oneone Fig 1.7"
> >>
> >> Here is some more information on the subject that may help
> >> inspire some of
> >> the great minds out there.
> >>
> >> In spite of all the unjustified criticism, the latest test
> >> will show, at
> >> least to the more open minded nuts,
> >> There is NOTHING inherently wrong with the tight PLL method
> >> as I have done
> >> it. It gives about as good of answers as anything out there.
> >> As I've implemented it, there are some disadvantages, because
> >> there is just
> >> so much one can do with a single Op amp design.
> >> If one does the calculation they will also see the OP amp is
> >> not a limiting
> >> factor in the performance of this method.
> >>
> >> AS I have said before, the disadvantage of my simple BB
> >> version that was
> >> tested, is that it is limited by the Ref Osc and the way
> it's freq is
> >> modified.
> >> The accuracy is limited by the fact the first simple BB
> >> version I built is
> >> an all analog system.
> >> That is solely because the frequency control I used on the
> >> simple version is
> >> the analog EFC input of the reference Osc.
> >> I've also pointed out, that is not a limitation of the
> >> method, there are
> >> solutions for that.
> >> Now I'm amazed that no one has had a New inspiration.
> >>
> >> Maybe a more direct approach will help some to see the next
> >> logical step. Using the same basic tight PLL method, make
> >> some of the unit digital. Do not modify the freq of the
> >> reference osc with analog, GET it yet? That way the device
> >> would be half digital without any of the analog
> >> shortcoming or the need to physically change the reference
> >> freq. Do I really need to explain more?
> >>
> >> Have fun
> >> ws
> >>
> >> ***************
> >>
> >>
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> >
> >
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>
>
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