[time-nuts] Sidereal timekeeping
Hal Murray
hmurray at megapathdsl.net
Wed May 18 04:01:48 UTC 2011
lists at rtty.us said:
> In a full sized wall clock, most of the power is to the motor. On a wrist
> watch - it depends on how well the watch is built.
Thanks.
I think that means that it's not silly to generate a PPSS (Pulse per Sidereal
Second) signal by counting to 364/365 of 32678 rather than letting a 15 bit
counter wrap around.
If "most" means 90% and we use another factor of 10 to implement the
compare/reset, that only drops the battery lifetime by a factor of 2.
Divide the target count by 2 and toggle one more FF if you need better
symmetry on the output.
-----------
Hacking the crystal adds another dimension to the hardware/firmware/software
tower.
Is there a term for that?
----------
The party line for something like this is that 1/2 the power goes into the
bottom bit. (assuming we are talking about the logic and not the motor)
I wonder what the power ratio (battery lifetime ratio) is for custom CMOS vs
say, 4000 CMOS, or C, or HC, or low power CPLD or ??? The CPLD might be
interesting since you don't have to drive external pins/pads. There is
probably some 4000/HC chip that includes a counter but would save power
because it doesn't bring the bottom bit or two out to a pin.
--
These are my opinions, not necessarily my employer's. I hate spam.
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