[time-nuts] Synchronisizing a 100MHz TCXO with Tbold
SAIDJACK at aol.com
SAIDJACK at aol.com
Tue Sep 20 01:07:50 UTC 2011
Bert,
one would typically limit the loop bandwidth to something much lower than
10KHz. Say 100Hz.
This way at 10KHz the ADF4001 would have no effect on phase noise, it would
be almost entirely determined by the TCXO itself.
This is because a 10MHz reference would have to have to be better than
-170dBc/Hz at 10KHz to not affect the output phase noise if the loop bandwidth
is >10KHz. This is due to the 20log(100/10) noise effect.
The loop bandwith should be set where the reference OCXO phase noise floor
with added 20dB noise intersects the TCXO phase noise floor. This will
typically be <<1KHz.
bye,
Said
In a message dated 9/19/2011 18:01:26 Pacific Daylight Time,
EWKehren at aol.com writes:
Peter, it will be difficult to degrade -138dBc/10kHz using a ADF 4001. I
have PLL's using selected $ 1.00 Xtals getting better than
-153dBc/10kHz.
.Axtal has units with -174dBC but out of most price ranges but I thought
you were looking at below -150,very doable with ADF 4001.
Bert
In a message dated 9/19/2011 5:53:22 P.M. Eastern Daylight Time,
krengeldatec at gmx.de writes:
Thank you all for your suggestions.
@ Attila:
I think your suggestion would be "a little bit"
too complicated. I dont want to write a dissertation :))
My idea was to simply get a low jitter out of the 100MHz
TCXO clocking the FPGA etc..
The fine TCXO I like to use is a AXLE20-12 from AXTAL.
I think its expensive enough for my experiments (about 100,- EUR) and it
also
got a electronic frequency control input as well as a even much
more expensive OCXO which would cost me 180,- EUR or more.
As I said as the ADCs are working in cascade they have to be
enabled and disabled as exact as possible to avoid sampling errors.
A jittering clock would do a bad job in that circuit while long time
stability is not a problem.
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