[time-nuts] sysclock source for AD9912 DDS?

[Michael Jensen]

Try to look on these designs made by me

http://rudius.net/oz2m/ngnb/vcopll.htm

Michael

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Fra: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com] På vegne
af Anders Wallin
Sendt: 30. december 2013 16:56
Til: Discussion of precise time and frequency measurement
Emne: [time-nuts] sysclock source for AD9912 DDS?

I've tested the AD9912 evaluation board:
http://www.anderswallin.net/wp-content/uploads/2013/12/dds_test_2013-12-30.p
ng

I want to use it with a 10MHz external input clock, but it looks like the
on-board PLL that generates a 1200MHz sample clock from my input isn't that
great, since I get strong side-bands on the output that are only 18-20 dB
down from the fundamental.

So it looks like I need to supply a clean 800-1000MHz clock to the DDS to
get a clean output. Any ideas/suggestions for generating this from a 10 MHz
sine?
Driving the DDS system clock from an expensive RF generator (e.g. HP 8648A)
would be possible but I'd prefer a PLL from 10MHz if it's doable
simply/cheaply.

Anders
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