[time-nuts] 5>10 doubler

[Charles Steinmetz]

Andrea  wrote:

>>But, what is the advantage between it and a couple of diode-connected
>>transistors with a full A-class (more linear, so less spurs) 
>>amplifier in front
>>of it?

>>If it's so, why use a nonlinear (or barely linear) gain stage to rectify?
>>Using just one stage means in general less phase noise output (but with
>>probably more spurs that can be filtered out), versus a more stage linear
>>amplifier (perhaps with strong negative feedblack) followed by a rectifier?

I replied:

>The "barely Class A" push-push doubler does not rectify the signal 
>-- it creates the second harmonic because of the primarily 
>second-order transfer characteristics of the JFETs.  The design goal 
>is to map the DC bias and the input signal to the portion of the 
>FETs' characteristic curve that has the best fit to a second-order 
>transfer function, while at the same time holding noise below the 
>design requirement.

Perhaps some pictures would be helpful (see below).  Figure 1 (top) 
shows an ideal full-wave rectified sine wave, similar to what is 
produced by a full-wave diode rectifier, a bipolar transistor 
push-push doubler, or a FET doubler driven into pinchoff (Class 
B).  Obviously, it is extremely rich in harmonics.  The second 
harmonic of the output (doubled) frequency is only 14dB below the 
desired signal, and a series of even harmonics stretches as far as 
the eye can see, diminishing only very slowly with increasing 
harmonic number.  (In practice, there will be a HF rolloff that makes 
things slightly better.  However, there will also be odd-order 
components, which an ideal full-wave rectifier would not produce.)

Figure 2 (bottom) shows waveforms from the simulation of my "barely 
Class A" push-push doubler, using a matched pair of J111 FETs (J310s 
perform almost identically, with the appropriate change in the bias 
resistor).  I purposely introduced a 10mV gate voltage imbalance in 
the simulation to model imperfect matching.  The red and magenta 
traces are the currents in the two FETs, showing a primarily 
second-order transfer characteristic.  When these currents are added 
by the push-push connection and put through a 4:1 (turns ratio) 
transformer into a 50 ohm load, the green trace results.  This trace 
shows the simulated raw output, without any traps.  Obviously, this 
is very much closer to a clean 10MHz signal than the rectified signal 
in Figure 1.

The 5MHz component is ~40dB below the desired 10MHz signal.  This 
depends strongly on how well the FETs are matched and on the layout 
and shielding.  J111s or J310s from the same lot, matched to within 
1mV, should do better than this (the 5MHz component from my 
breadboard circuit is below -45dBc, without any traps).  The other 
visible distortion products, and their levels, are:

15MHz    -75dBc
20MHz    -45dBc
25MHz    -100dBc
30MHz    -75dBc
35MHz    -100dBc   (all figures are approximate).

The breadboard circuit performs similarly (the 15MHz component is 
about 10dB lower from the breadboard, so I needed traps only at 5, 
20, and 30MHz to get all spurious responses below -80dBc).

As I noted before, the "barely Class A" circuit is not materially 
noisier than a FET push-push doubler that is run into Class AB or B, 
but it has MUCH lower spurious outputs and, therefore, does not need 
the sort of aggressive filtering the Class AB/B circuits need, 
avoiding the increase in phase noise and other problems associated 
with aggressive filters.

Best regards,

Charles

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