[time-nuts] OCXO PLL gains?

[Bob kb8tq]

Hi

I’m sure there is a closed form solution somewhere out there that includes noise. It is 
more common to do it with simulation by one method or another. You normally have a 
lot going on in a PLL. 

Simple answer is - less gain = less bandwidth.  If what you have is too wide, cut it down. 
If you have too much of a peak with just P, check for lag in the circuit. It is very normal 
to have 3db of noise peaking.  

It’s generally best to run through a gain / stability calculation once you go to P-I. It will 
not help much with the noise side of things but it will help with getting the loop to lock. 
It will also give you a good idea of how much gain peaking you may have with a given 
configuration. There are a ton of app notes and text books out there on that side of it. 
Gardner:

https://www.amazon.com/Phaselock-Techniques-Floyd-M-Gardner/dp/0471430633 <https://www.amazon.com/Phaselock-Techniques-Floyd-M-Gardner/dp/0471430633>

is an oldie but goodie in this area. 

Bob

> On Feb 1, 2019, at 1:11 PM, Anders Wallin <anders.e.e.wallin at gmail.com> wrote:
> 
> Hi all, is there are rule-of-thumb or simple paper/presentation of how to
> choose PLL-gains?
> 
> I have a phase-detector that gives out a slope of roughly 1 V/rad, followed
> by an op-amp circuit with proportional, integral, and double-integral gains
> summed into one voltage [0, 3.3V] on the tune-pine of the OCXO ( +/- 0.6
> ppm pull-range, from datasheet).
> 
> So far it locks with only P-gain, but the phase-noise (and ADEV) shows a
> 'bump' somewhere between 10 and 100 Hz offset from the carrier.
> I tried the integrator with a time-constant of 1/16Hz using R 100k  C 100n,
> but it wouldn't lock.
> The thinking was to put the integrator time-constant about where the
> free-running ADEV turns upwards from a 1/tau slope.
> 
> So far I didn't enable the double-integrator - not sure if it's worth the
> trouble or not..
> 
> thanks,
> Anders
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