[time-nuts] AD9912 DDS frequency resolution measurement?

[Anders Wallin]

Hi, thanks for the comments. A bit more details about the boards and the
measurements.

DDS board1 is an AD evaluation kit AD9912A/PCBZ which is fed a 1 GHz SYSCLK
generated on another evaluation board EVAL-ADF4350EB1Z.
The FTW is written over SPI-bus from an Arduino.

DDS board2 is an ARTIQ Urukul (https://github.com/sinara-hw/Urukul/wiki)
which takes a 100MHz ARTIQ system clock as input and multiplies it to 1 GHz
SYSCLK.
On this board we tried "readback" of the FTW, and we did not find anything
strange, i.e. if we write an odd FTW (ending in LSB '1') we readback the
same odd value (and vice versa for even FTW).
However the output frequency behaves as if the LSB is zero.

Measurement system1 is a Microsemi 3120A with TimeLab (including frequency
counter license). I forget the 1s ADEV of the DDS, but let's say it is
2e-12. The reported frequencies are 1h averages.
Very roughly if we go down by 1/3600 from 2e-12 we should have about 6e-16
of noise at 1h. The '2 LSB' step we see 7.1 uHz @ 10 MHz is 7e-13
fractional, or 1000-fold larger than the expected noise. The 3.55uHz step
expected from the DDS datasheet
 is 500-times more than the noise level.

Measurement system2 is a PICDIV-board programmed to output 1PPS from 10MHz
input. The PPS is compared to a reference-PPS (coherent with the 10/100MHz
DDS SYSCLK reference) using a 53230A counter. The PPS-reading has roughly
50ps RMS noise, giving a 1s ADEV of maybe 9e-11. The reported frequencies
are 2 hour averages. Assuming white phase-noise the ADEV @ 7200s should be
around 1.2e-14 or 30-fold lower than the expected 3e-13 step (The PPS
drifts 1.3 ns/hour for a frequency offset of 3.55e-13).

If someone else out there has the bits and pieces to reproduce these
measurements I would be very interested to see the results!

Anders


On Mon, Feb 18, 2019 at 7:01 PM Magnus Danielson <magnus at rubidium.se> wrote:

> Hi Anders,
>
> On 2019-02-18 14:47, Anders Wallin wrote:
> > Hi all,
> > We've tried to measure the 1e9/2**48 = 3.55uHz frequency resolution of an
> > AD9912 DDS (clocked at 1GHz SYSCLK), but found that the output
> corresponds
> > to an FTW with the LSB set to zero.
> > Results around 10MHz output, where we expect a step of 3.55 uHz for each
> > step of the FTW, but instead see a step of 7.1 uHz every second step.
> > https://drive.google.com/file/d/1U5nbg2RSOpVRa8VLOJ6bCWsyihcSBhBZ/view
> > https://drive.google.com/file/d/1c6CoQIWzRoM4y8CLoRLhi7sh2pMCywwo/view
> >
> > has anyone else worked a lot with the AD9912 and verified the frequency
> > resolution?
> > (I can describe the setup&measurement more in detail, but we believe we
> > know roughly what we are doing and tried this with two different AD9912
> > boards and two different measurement systems)
>
> OK, I agree that it looks like you loose the LSB. You know what you are
> doing for the measurement of frequency, so for the moment I'll assume
> that this is not where you got your error.
>
> Now, how did you set the DDS up? Have you checked that the actually
> written registers had the setting stepped?
>
> Did you used some finished code? Did you write your own? Have you read
> out and verified the bit positions? Have you checked all other setup bits?
>
> I'll happily help verifying the setup part.
>
> Cheers,
> Magnus
>
>
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