[time-nuts] AD9912 DDS frequency resolution measurement (and OT LTC6957)

[Gerhard Hoffmann]

Am 19.02.19 um 12:29 schrieb Bo Hansen:
> Hi
>
> I have experience with the AD9912 in this H/W and S/W implementation: <http://rudius.net/oz2m//ngnb/dds.htm>
>
> But I must admit that I personally haven't measured the minimum frequency step size. Poul-Henning Kamp, among others, is using one of the AD9912 DDS units and observed a similar error, I think, that he has solved in this S/W: <http://phk.freebsd.dk/misc/ftw.c>
>
> Whatever applies list the FTW values and calculate back to the real frequency and see if the frequency change is correct.
>
> A friend of mine has a x96 multiplier from 108 MHz to 10 GHz but we don't have access to any counters capable if measuring the difference.
>

Actually, you can measure that with a voltmeter.

Force the frequency tuning word to 0x0000 0000 0000 and verify that the 
sine output stays at 0

or wherever it was if you already have a phase offset.


Then set the f-word to 0x0000 0000 0001 and check after 19.5 hours if 
the sine has crept by 90°.



BTW I've opened a case in AD's engineering zone this weekend about the 
LTC6957 sine-to-square chip.

< 
https://ez.analog.com/clock_and_timing/f/q-a/107463/ltc6957-ims-3-output-oscillations 
     >


When it has no load at all, then connecting an inch of wire to one of 
the outputs makes the other

output show some oscillations. Maybe the data sheet needs a minimum rise 
time or minimum

input frequency spec. 1 MHz at 2Vpp  is already slow.

Not a show stopper, but that does not build confidence. Impressive 
output rise time for CMOS, nevertheless.


And the AD9901 phase comparator I mentioned there at EZ was not a real 
one from AD. :-)

It was a tiny corner in a $2  64-FlipFlop Coolrunner CPLD and half a 
page of added VHDL.


best regards,

Gerhard