[time-nuts] Atomic Clocks: It is important that they keep good time, Part 1
Rice, Hugh (IPH Writing Systems)
hugh.rice at hp.com
Fri Jan 4 03:42:04 EST 2019
The clock display on a HP Cesium Standard is a bit of a gimmick. The legend I was told: An Admiral was touring a nuclear submarine, and was being shown the "Atomic Clocks" in the navigation section, and said: "If the Navy is going to pay 40 grand for an atomic clock, I damn well better be able to set my watch by it." And so the need for the clock display was born. (There is likely almost nothing true in that heavily embellished story....)
The 1PPS output, clock display and backup battery were new features added when HP upgraded the 5060A to the 5061A in the early 1970s. The 1PPS circuit was pretty cool. Dividing the 10MHz signal down to a narrow 1 pulse-per-second signal was straightforward, but they added a delay circuit, actuated with a series of thumbwheel 10 position switches, that would allow you to program a delay from 0.1uS to 1 second. Essentially, set the clock (1PPS signal) to match another reference to within one cycle of the 10MHz input, or 100 nano-seconds. The cosmetic human readable display was driven by the delayed 1PPS signal. Since the clock is "only" human readable, their accuracy is essentially +/- 1 second. But those "in the know" realize that when the clock switches to the next second, they are accurate to +/- 100 nano-seconds. The propagation delay through the display electronics would be tactfully unmentioned. That should be good enough for the Admiral.
The first 5061A used an analog style clock manufactured by "Patek Philippe". But it wasn't too many years before Patek Philippe obsoleted the analog electro-mechanical clock, and HP had to design a replacement. This is the more common LED digital display seen on later 5061As. The catch: HP needed to support the old 5061A's that had the analog clock. So the new LED assembly was designed to be backward compatible service and support component too. Some poor engineer had to come up with a solution that fit the electronics in the round hole used by the Patek clock. 3 circular PCAs were used, electrically connected with pins from one PCB to the other, so it would be a drop in replacement. It was a hack of epic proportions. Hard to manufacture, expensive, power hungry. But it worked and was reliable.
As part of the 5061B product, we wanted to cut clean from the baggage of the 5061A past, and didn't have to make all our assemblies backward compatible. My job as a brand new engineer was to design a sensible clock display. Cheaper, easier to build, using less power. (I recall that the power drain from the clock/LED assembly was significant enough to materially impact the battery backup time.)
This was my first ever digital design, and I had a great time coming up with a circuit that would go from 1PPS to a hours, minutes, seconds digital display, including a feature that would allow you to easily set the clock by pushing buttons on the back side of the PCA, by sticking a small screwdriver through the cooling holes on the top cover. I choose to use a LCD display, for its low power. I agonized for weeks on what logic family of digital parts to use. LS-TTL? 4000 CMOS? I eventually choose the 74HC series of CMOS components. They were fairly new to market, which I hoped to indicate they would have a long life, since we were going to build the 5061B "forever". And all the components I needed were catalog parts. (Counters, display drivers, AND gates, etc.)
In my youthful ignorance, I made a few mistakes that Roberto had to clean up later. First, our PC Layout team was experimenting with new auto routing software tools, and choose this design to experiment on. Low frequency, low power, simple. What could go wrong? The auto-routed layout worked fine, even though the routing between the components looked like the output of a random number generator. (If you download the scans of the 5061B manual I uploaded, you can see the random trace routing in the picture of the clock assembly.) Next, I didn't appreciate that the 74HC logic family was pretty fast, with snappy rise and fall times. Capacitive coupling of signals between traces due to fast edges was a foreign concept to me. Finally, in my overzealous quest to save every microwatt in this design, I used 100K resistors for voltage dividers and pull downs, rather than a more sensible 10K or 1K values.
My clock display that worked so nice in all our prototypes (1 sample), turned out to be capable of catching a stray glitch now and then, since the 1PPS signal wound all over the PCB before it was input to the first IC. After a few years of production, some customers complained that the clock would sometimes skip a second.
The Atomic Clock didn't keep accurate time!
I had moved on from PFS production engineering to Frequency Counter Production Engineering Management when this was discovered, and Roberto called me up and gave me hell about my crappy design that he had to clean up with a new PCB layout. New layouts were expensive (a few thousand dollars), and a big deal on a low volume product. To make matters worse, I was now in management, and was by definition incompetent and an idiot. The new manager lobotomy and such. And a traitor or PFS to boot, because I left the team. Roberto was not happy with me. I apologized for my incompetence and thanked him for cleaning up my mess. I managed to hold my tongue and not remind him he was the lead engineer, and had design reviewed and approved all my work.
The moral of the story is clear: If you put a display on an Atomic Clock, it really needs to keep accurate time.
Part two is another clock story, but I'm not the goat this time.
Happy new year,
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