[time-nuts] GPS 1PPS, phase lock vs frequency lock, design

[Hal Murray]

> 2)  I think I understand this.  Further I will have to understand  what the
> optimal PLL BW is in light of the OCXO short-term ADEV being potentially
> better than GPS 1PPS with correction.  Perhaps this means the loop BW should
> be on the order of a milliHertz, if it takes 1000 seconds for the OCXO to
> drift worse than the GPS.
> 3)  The nominal design uses a low-noise 16-bit
> current output DAC, your point regarding LDAC to enable precision (in time)
> updates to the output would enable a more-rigorously correct loop.  I am
> considering using two DACs, one scaled to the OCXO tune range of 5V or 10V,
> one scaled with much smaller range to provide additional bits of resolution,
> summed to provide the extra bits necessary. Does your sigma-delta modulator
> comment apply to the numbers written to the traditional 16-bit DAC as a
> dithering technique?  I understand your comment regarding a direct
> implentation of an SD 1-bit DAC, again dithering the digital input presumably
> to "smear" quantization noise? 

Don't forget to consider the stability of your DAC.

If it drifts slowly, the PLL will track the drift.  But that's slow relative 
to the PLL bandwidth.  If your PLL time constant is 1000 seconds, your room 
temperature probably changes faster than that.
 


-- 
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