[time-nuts] Question for my new GPSDO

[Achim Gratz]

Tobias Pluess writes:
> Assume a timer is clocked with the 10MHz clock. The timer overflows
> when it reaches 9999999 (=10e6-1). Further, this timer is used to
> generate the 1PPS pulse output: each time when the timer reaches the
> value of 0, a pulse is generated on one of the output pins. Since this
> happens all in hardware, this should be fine and shouldn't have jitter
> introduced (e.g. by interrupts or whatever).

I don't know in detail about the particular part you are using, but I
doubt that it is actually using an asynchronous clock into the hardware
counter.  The more typical arrangement is that it gets registered to
some internal clock before the timer hardware deals with the signal
(often via two stages to get metastability issues out of the way).


Regards,
Achim.
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