[time-nuts] low power divide by 5

[Mike Ingle]

Hi,

As suggested by others, another approach could be to use a cpld of some
type, for example look at the lattice mach  or the old cool-runner
varieties.
You can usually DDR the clock.  This should give the same symmetry as the
input clock.  With a 50% duty cycle 50MHz input this should give a 10MHz
50% output;
In VHDL for example:

process(clk)
begin
if (rising_edge(clk) or falling_edge(clk)) then
  if (cnt < 5) then
    cnt <= cnt + 1;
  else
    cnt <= 0;
    divided_by_five <= not(divided_by_five);
  end if;
 end if;
end process;

and there are usually built in DDR IP's from the vendors.

-- mike

On Wed, Jul 1, 2020 at 8:50 AM Robert LaJeunesse <lajeunesse at mail.com>
wrote:

> Take a look at the "modified" shift-register like counter in the attached
> jpg file. When simulated online it behaved as expected for a divide by 5. I
> believe it also is self-clearing from illegal states, but the other
> simulator I tested that in wasn't good for documenting the design.
>
> Bob L.
>
> > Sent: Tuesday, June 30, 2020 at 6:47 PM
> > From: "dschuecker" <Detlef.Schuecker at dschuecker.de>
> > To: time-nuts at lists.febo.com
> > Subject: Re: [time-nuts] low power divide by 5
> >
> > Hi,
> >
> > a divide by five should possible with a synchronous state-machine made
> > of 3 ( sufficiently fast-) JK-FlipFlops.
> >
> > All 3 FFs are clocked with the input freq. , the outputs of the FFs are
> > fed back to the the JK-inputs,  the divided freq. is output of one of
> > the FFs.
> >
> > Additional constraints: no external ANDs or ORs or NOTs, the
> > state-machine does not get stuck in the 3 unused states.
> >
> > This turned out to be a very interesting problem and I do not yet come
> > up with a solution. Maybe there is none. Analytical solutions all
> > failed, I will try a brute force enumeration attack tomorrow.
> >
> > lots of fun !
> >
> > Cheers
> >
> > Detlef
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