[time-nuts] Assistance needed to understand some V_OCXO stability concepts.

Thu Oct 1 14:19:22 UTC 2020

Thank You to all for the kind invitation to the group!
 I will try to be as brief as possible in the description - The unit is
quite complex so I may not succeed with few words..

The block diagram attached - *JoNo GPSDO Block diagram.pdf*

A Nucleo STM processor manages it all. A 7inch NEXTION touch display forms
the front panel and main control input. ( upper and lower left in diagram).
Upper part of diagram - 16Bit DAC controlling the + and - EFC inputs to the
HP-00105-5013 5MHz OCXO. The latter then into buffer, then a diode doubler
to 10MHz, then filtered via LC and Crystal filter, and buffered into
splitters and to panel connectors.
Lower center of diagram - 2 x UBLOX M7N GPS modules - GPS1 and GPS2, each
connected via a 3dB hybrid coupler to a common LNA, and to the antenna.

GPS1 - This GPS serves a very specific purpose.
  The NAV_CLK message in the data stream indicates the clock bias, or by
how much the ref_clock time derivation deviates from the Constellation
clock ( in nanoseconds)  If the 26MHz is EXACTLY 26MHz, then the clock bias
drift is zero, and drifts according to the amount the 26MHz clock is of
frequency. So, if the 10MHz OCXO is exactly 10MHz, then the clock bias
drift is zero. But this is to a nanaosecond resolution, so not good enough
to control the 10MHz osc to the parts per trillion domain..
However, the drift rate is VERY useful to assist in ensuring that the OCXO
is locked to 10MHz, and not to some multiple of the phase detector wrap
around delta. This was the only way I could ensure this fact, without
having Hi resolution, accurate frequency counters, etc.   I also use this
GPS PPS output as a programmable ( in 0.1Hz steps) frequency generator up
to 20MHz ( albeit with jitter - good enough for general use as an HF
signal Gen..)

GPS2 - This GPS has its 26MHz oscillator intact and I use the 1PPS pulse to
gate the phase detector. The 1PPS signal first goes to a programmable
digital (Dallus) delay line. A GPS message gives the predicted jitter on
the PPS signal, and so the delay line is pre-programmed with this delay,
for the 'next' 1PPS pulse - this substantially reduces the PPS jitter, and
the resultant phase detector sawtooth output - see *Sawtooth
Correction_1.jpg*
The 'de-jittered' 1PPS signal now forms the gate for the phase detector, a
7474 D type flip-flop and nand gate. The ref clock to the phase detector is
the OCXO 10MHz divided by 10 = 1MHz.
The resultant pulse varies from '0ns' to 1000ns, and is stable at a value
if the 10MHz clock is stable and accurate.
That pulse is converted to a DC level and read by the Nucleo A/D ( 12bits)

The Nucleo then attempts to drive the DAC so that the phase detector
voltage output sits at 1.8volts or thereabout, and endeavours to keep it
there. The phase detector output voltage is filtered by an inital 32tap
FIR, and then when initially locked, by subsequent IIR filters each with
greater filter coefficients.

An attached 22hout plot shows the following:  *(22hour plot.jpg)*
Top Plot is oven volts ( an output from the OCXO oven controller)
Center Plot shows the Phase detector setpoint in green - 1800 mV and the
actual detector output voltage in red.
The lower plot shows the DAC output in millivolts - each of the tiny steps
are 1mV.

In light of the Oscillator KV of 0.03 Hz/volt, a 1mV change on the EFC
input should then change the OCXO frequency by 0.00003 Hz. ( being perfect
here..).

Am I correct that that is a 3ppt variation?
So, in the plot, the DAC voltage changes approx 10mV between time 46000sec
and 56000sec, ie 10mV in 10000sec ( 2.77hours).
This implies the frequency change was 10mV X 0.00003mV/Hz =  0.0003 Hz -
does this equate to 30ppt ??
Is this feasible??? 30ppt??  Is that good?

This also implies that over the 56000 seconds (15 hours) the DAC voltage
changed 36mV = 0.1ppb ???
If this is all true and correct, I still am worried about the validity of
my assumption of what the change in DAC voltage actually means-
It changed 36mV over the 15 hours, but did it change to compensate for the
change in temperature ( as seen by the change in oven control voltage), and
if so, is it then not possible that in fact the oscillator frequency did
not actually change by the 0.1ppb - ie, the oscillator actually 'did not
change', because the temp variation tried to make it drift, but the DAC
output voltage from the control loop corrected it and so it remained
unchanged....???!!

So, I am a little lost in understanding how to characterise this animal,
and how to measure what. I get the feel its performance is actually very
good, but I don't know why, nor how to defend that statement.

HELP!!

Also attached, some photos of the unit -
front panel and layout - *Main Page.JPG*
There is also an Analogue Devices DDS internally - fed from the 10MHz
ref-Clock - capable of 1KHz to 50MHz output, in 0.1Hz steps.
There is a control page for the various sig-generators as well -* Front_SETUP
Page.jpg*
Internally, the picture shows the shielded modular construction of all the
doublers, filters, GPS modules, synthesizers, etc - with the OCXO exposed -
*TOP_open.jpg*
And with some more thermal insulation of the oven - *TOP_Insulated OCXO.jpg*

Thank you all for your time!

Some gentle guidance will be very much appreciated.
regards
Joe

On Thu, Oct 1, 2020 at 10:33 AM Joe & Gisela Noci <jgnoci at gmail.com> wrote:

> Good Morning all.
> I am new to the group, very green as to how the group/mailing, etc works,
> so if I mess up, please put me straight, gently...!
> I do not have much experience or knowledge in this field, but have spent
> the last year or so building a GPDSO and need some help in understanding
> the results I get - they seem to good to be true, so I suspect it's not
> true!
> I have built the unit based on the Brooks Shera concept, with some changes
> in collaboration with Jeff, K6JCA.
> To describe it would be best done by means of a block diagram ( can I just
> add a PDF as an attachment to this mail and will everyone then see it?). In
> essence - a UBLOX M7N GPS provides a 1PPS signal which controls a pulse
> width detector, fed from the HP_00105-6013 OCXO ( pulled from a defunct
> HP-5061A) . This pulse width is converted to a DC level, into a D/A. A uP
> then drives a 16bit DAC to control the Varicap drive to the OCXO.
> I have measured the KV of the OCXO to be close to 0.03Hz/volt.
>
> The DAC drive is derived for a set of software filters, first is a 32tap
> FIR, for initial stabilization, then into IIR filters of increasing time
> constants, 30sec, 100sec, 200sec, 400sec.
>
> I log plots of the pulse width detector, DAC voltage, Oven temp, and many
> other parameters.
> I do not have any fancy equipment to measure Adev, etc, nor any accurate
> frequency counters...
> NOTE - The OCXO is a 5MHz unit, but I double to 10MHz and the ref clock to
> the pulse width detector is 10MHz/10 = 1MHz. So the pulse counter has a max
> period of 1us.
>
> I understand the  KV of the OCXO works out to 3ppt / millivolt (from the
> 0.03 Hz/volt).
> When I run the unit, it locks very well, and while running with IIR4
> active ( 400sec) is observe the following:
> The DAC output voltage curve shapes closely resembles the temp control
> voltage to the oven - as I would expect.
> Over a 24hour period the oven control voltage varied by 0.5 volts. The
> total DAC voltage during this varies by 36millivolts ( Is that 0.108ppb in
> delta freq?)
> Over a specific period of 3 hours ( afternoon), where the temp control
> voltage varied by less than 200millivolts, the DAC output varied by
> 10millivolts ( is that 30ppt ??)
>
> Please forgive my questions - I lack the knowledge to know if I am asking
> the right questions!
>
> I can post some plots if it will help folk explain what I should be asking!
>
> Thank You
> Joe
> V51JN, Swakopmund
> Over a
>
>
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