[time-nuts] Need help phase locking with small offset

[Stewart Cobb]

Thanks to all for your comments. To minimize crosstalk, the plan is to
clock the entire FPGA from the 100 MHz OCXO. The other inputs will be
sampled at the input pins by D flip flops clocked by the main clock. There
will be some unavoidable interaction between the CLK and D inputs to the
flip flop, but the White Rabbit project seems to have demonstrated that
this is manageable. When I get results, I'll pass them along.

Cheers!
--Stu