[time-nuts] Phase Noise and ADCs

[John Ackermann N8UR]

On 9/26/20 9:33 PM, John Miles wrote:

> One consequence of charge retention is that when the input signal is in the first Nyquist zone, meaning below fLO/2, no net frequency translation occurs in a sampler.  There is no mixing going on, hence no reciprocal mixing either.  The sampler's zero-order hold characteristic passes the captured input signal straight through to the output.  Because your ADC's front end is a sampler, this is the condition that applies when you digitize a 10 MHz input signal with a 122.88 MHz clock.  About 13 times per input cycle, a sample of the 10 MHz signal is captured and transferred to the hold capacitance for eventual readout on the data bus.  Any jitter that's present on the 122.88 MHz clock will be transferred as well, but it will be attenuated by 20*log10(12.288) dB because each clock cycle is responsible for capturing only about 1/13 of each input cycle.

That actually makes a lot of sense.  Thanks very much!

John