[time-nuts] Re: HP Z3801A info needed - 1PPS interface

[Bob kb8tq]

Hi

> On Oct 5, 2021, at 3:11 PM, ed breya <eb at telight.com> wrote:
> 
> I've been doing a bit more work on the far from finished Z3801A project, trying to button things up. It has been sitting for years all opened up (but running), with temporary pieces and cables and wiring hanging out every which way. The next piece I want to get going is the 1 PPS interface, to provide the signal out, and to run the clock. In the manual it says the 1PPS signals are on the DB-25 connector, in differential "pseudo-ECL" form, but that's all - no level or common-mode info is provided. Online searching the term seems to indicate it's just PECL - Positive ECL running from +5 V, with everything shifted up accordingly. That's just fine (and easy to implement), as long as I know what to expect. I figured I'd check here to see if that's correct, or if it means something else in the Z3801A context. I'll find out eventually when I start fooling with it, but right now it's buried deep in the guts of the box, so not easy to scope out yet until I start hooking it up and designing the interface.
> 
> A related question is, is there any particular generally accepted or favorite spec or description of the 1PPS signal output from the BNC? I'll probably make it 0/+5 V out, fairly strong, with the leading positive edge being the official tick mark. The clock will use a softened up version. The DF will be whatever the Z3801A puts out.

There are a lot of posts in the archives about 1 pps signals. The basic choices:

1) Source terminated 5V  “CMOS” signal. The driver needs to handle a net 100 ohm load. (50 ohms
at the source and 50 ohms at the load). If the load is terminated, you will see a 0 to 2.5 V signal there. 

2) Not source terminated 5V (or 3.3V) “CMOS”. The driver is built to put out enough current to take a 
50 ohm load to 5V (or 3.3). You now get a 5V logic signal on the far end when it’s terminated in 50 ohms. 

3) Doubly terminated 5V CMOS. The driver puts out a 10V signal and can handle a net 100 ohm load.
The source is at 50 ohms and the load is at 50 ohms. You get a 5V logic signal into the load. (and 10V
if you forget the termination … yikes ….). You pretty much never see this approach used. 

Both 1 and 2 can be implemented with pretty normal logic gates. Some number of fast gates in 
parallel will be able to drive whatever load you decide on.

Bob


> 
> Ed
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