[time-nuts] Re: Death of a Capacitor

[nuts at lazygranch.com]

Did you mean low ESR?

A good switcher design will have an undervoltage lockout. 

There are a few groups that test a chip before release. One is the
applications group. They will put the DC/DC on a bench supply and
slowly dial up the voltage. Everything needs to behave at any voltage
withing specs. Then they will use a home brew P pass fet pulser to jam
the circuit. That could catch a latch up condition. Depending on the
company, they will short adjacent pins. This is to mimic a clumsy
engineer or tech with a scope probe. Mind you passing that test isn't a
requirement but often you will pick a pin layout that allows for such
nonsense. 

The applications group may short a pin to ground, one at a time. If the
chip has an internal fet, the designer may elect to current limit the
device. This is a gray zone in the design since circuitry is being
added that should not be needed in the real world. The idea behind this
protection is during the design-in phase the customer might feel a
little nervous about the part if they accidentally destroy one. Yeah
even if it is their own fault. Better to have the designer to say "Whew
that was close...ah it still works." Some companies don't go this far
with the idea being you give (or sell) an evaluation board so there is
nothing for the customer to probe.

The above may be repeated with a pin one at a time to a hard supply.
Personally I think that is ridiculous and never designed for the case
unless it was a current limit. I will say that because these chips have
logic state machines in them, it is possible that pulling some pin high
or low might get the state machine in an unanticipated condition.
Ideally the state machine has no uncovered state that will lock up. I
would design in a watchdog timer. Even if things were crazy, it would
only be for a short time period. 

You read about wall warts catching fire. You don't want to be that
person who created that product.  

On Mon, 27 Sep 2021 10:22:21 -0400
John Ackermann N8UR <jra at febo.com> wrote:

> Indeed, Dana.  Texas Instruments has a nice "designer workbench" for 
> their switching regulators like the TPS53400 to help select the 
> components.  Using that worked much better than trying to follow the 
> data sheet circuits.
> 
> I also found that high ESR caps, particularly on the output, are 
> important.  And also that you don't want to slowly ramp up the input 
> voltage for testing, as the thing will start sqealing if fed with 
> voltage way below the output.  You want a quick start at the working 
> input voltage.
> 
> On 9/27/21 9:56 AM, Dana Whitlow wrote:
> > One other thing to consider with LDOs:  some types can go  unstable
> > and oscillate with
> > the wrong (combination of) capacitors on input and output.  So any
> > time you design in
> > an LDO, it is important to closely scrutinize the datasheet and
> > application note(s) and
> > heed their warnings.  Unless you like rude surprises, that is :-)
> > 
> > Dana
> > 
> > 
> > On Mon, Sep 27, 2021 at 3:16 AM nuts at lazygranch.com
> > <nuts at lazygranch.com> wrote:
> > 
> >> I've only designed one LDO as a discrete chip (as opposed to a
> >> portion of a chip where performance just has to be good enough),
> >> so I have no guru status. That said, what spikes pass through a
> >> LDO if you do it right is simply a capacitor divider comprised of
> >> the capacitance across the pass device and the filter capacitor.
> >> This is a bit more predictable with a PFET pass than a PNP.
> >>
> >> https://www.analog.com/en/products/lt3045.html
> >>
> >> You can see the PSRR after a point (200kHz) rolls off and appears
> >> to flatten. I assume the error amp is out of loop gain. It goes
> >> flat for a while. The idea here is the drive on the pass device is
> >> constant and just maintains the DC voltage. The AC rejection is
> >> mostly due to capacitance ratios. This being a bipolar pass device
> >> there is some secondary effect here where after 2MHz the rejection
> >> improves then goes flat again.
> >>
> >> The bipolar pass control is harder than MOS since you are trying to
> >> keep the device out of saturation. That is besides the error amp
> >> there is some sort of anti-saturation circuit controlling the
> >> drive on the pass device.
> >>
> >> My thinking here is small signal. If you have huge spikes the
> >> performace even in the region where you do have loop gain can be
> >> nonlinear. For example the error amp can be slew rate limited.
> >>
> >> This looks like fine performance given the chip only draws 2.2mA.
> >>
> >> Just trawling the interwebs I found this on the TI website:
> >> https://training.ti.com/ldo-architecture-review
> >> At about the 18 minute point he goes into the regions of PSRR.  I
> >> poked around so I can't vouch more all of the talk,
> >>
> >> .
> >>
> >> On Sun, 26 Sep 2021 18:21:36 -0400
> >> John Ackermann N8UR <jra at febo.com> wrote:
> >>
> >>> I got some interesting and unintended data today. I was measuring
> >>> low phase noise oscillators using a set of power supplies I just
> >>> finished putting together.
> >>>
> >>> The configuration is ~24 VDC into a TPS-53400 switching regulator
> >>> that outputs 19.2 volts at up to 3 amps.  That output is fed to
> >>> separate regulator boards for each oscillator.  Those boards each
> >>> have an LT-1086 linear pre-regulator that drops the input to
> >>> about 17 volts, which then goes into an ultra-low-noise LT3045A
> >>> outputting 15 volt to drive the oscillator.  So there are two
> >>> linear regulators and lots of caps, inductors, and ferrite beads
> >>> to isolate the oscillators from the switching supply.
> >>>
> >>> Due to an error by an assembly tech who will remain nameless, the
> >>> wrong electrolytic was installed on the output side of the
> >>> switching regulator.  It should have been 33uF at 50 volts, but
> >>> what got installed was 330 uF at 16 volts, so it was rated below
> >>> the operating voltage. (I was building two boards at the same
> >>> time, one for 5V and one for 19.2V. Apart from the voltage
> >>> setting resistor, the only difference between the two was the
> >>> output cap.  I managed to swap them.)
> >>>
> >>> I tested the system on the bench for 24 hours and everything
> >>> worked fine, so I buttoned up the enclosure and started a 4 hour
> >>> data capture. About 70 minutes in, the electrolytic became very
> >>> unhappy and whatever it turned into caused the switcher to start
> >>> spewing all sorts of crud. The regulator kept working (sort of)
> >>> through the end of the run, but when I came into the lab the next
> >>> morning it had shut down completely and troubleshooting showed
> >>> that the cap had shorted at some point after the run completed,
> >>> and the regulator chip went into shutdown.
> >>>
> >>> Attached are a plot of frequency showing the whole run with the
> >>> very obvious change when the cap failed, and another zoomed view
> >>> of the critical moment.  The failure was very abrupt with no
> >>> visible lead-in.
> >>>
> >>> What I find interesting is that all that crud got through not one,
> >>> but two linear regulators, one of which is touted for its
> >>> extremely high PSRR (and I did my best to follow the recommended
> >>> PCB layout for that chip).  That must have been one ugly 19V line
> >>> when the cap went...
> >>>
> >>> John
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