[time-nuts] Re: Low Phase Noise 10 MHz bench signal source sought

[Bob kb8tq]

Hi

These days a PLL is going to either be analog or digital. If it’s 
analog, you get into size constraints related to capacitors
as you go to lower crossover frequencies. With digital, you
get into all of the noise issues that any digital circuit will have.
(Yes, they can be addressed but it’s not easy at very low
offset frequencies). 

Regardless of design, you will always have some noise peaking.
> 89 degree phase margins can help with this, but they bring
in other problems. Setting the phase margin and other parameters
is either a mathematical design process or done with simulation. 
It can be very frustrating doing it by trial and error. I still find 
Phaselock Techniques by Floyd M Gardner to be a good reference 
on this stuff. 

The normal PLL control loops are fairly low order filters. If you
go high order, loop stability (and peaking) becomes difficult
to handle. Because it’s a simple filter, things like close in spurs 
will only be attenuated by some finite amount. 

So yes, you will have issues. Dealing with those issues means 
an area ( = range of offset frequencies) that are not as nice as you
might wish. That’s just the way the real world works. 

Bob

> On Apr 3, 2022, at 8:14 AM, ew via time-nuts <time-nuts at lists.febo.com> wrote:
> 
> There is a lot of talk of Rb's and OCXO's  and using an OCXO for clean up. Very little about the clean up loop. It is key for overall performance. We are working on it for quite some time and are not happy with the results. On list off list would greatly be appreciated.                                                      Bert Kehren          
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