[time-nuts] Re: +1/f of transistors

[ghf at hoffmann-hochfrequenz.de]

Am 2022-04-10 18:09, schrieb usenet at teply.info:
> On 10.04.22 04:47, ghf at hoffmann-hochfrequenz.de wrote:
>> Am 2022-04-09 20:35, schrieb Lux, Jim:
>>> On 4/9/22 10:03 AM, usenet at teply.info wrote:

>>>> Recently I was discussing some measurement results with my 
>>>> colleagues as we're trying to come up with a low noise JFET which 
>>>> can successfully be integrated into a SiGe BiCMOS process, and quite 
>>>> often we're also struggling to identify why exactly variant A has 
>>>> significantly lower noise than variant B, or why a new approach does 
>>>> not improve noise the way it was expected.
>>>> So from a manufacturing process design point of view, achieving low 
>>>> 1/f noise indeed is closer to sheer dumb luck than the proverbial 
>>>> "more art than science" suggest.
>> 
>> 
>>> This is very, very true. Some manufacturers get very low noise or 
>>> very
>>> low leakage (or both), essentially by being "lucky".  From what I've
>>> been told, there's no good models, nor predictions - so people share
>>> "lore" of "if you get these 2Nxxxx FETs from the mfr in England,
>>> they're really good" until they aren't.   There isn't enough market
>>> for these, so I suspect research money to "solve the problem" isn't
>>> available.
>> 
>> Buy a life time supply while they are available. One reel will 
>> probably do.
>> 
> Unfortunately, that's not always an option. Sometimes you only learn
> that Part A is exceptionally good only when it isn't anymore. One of
> our customers got bitten by that, relying on parts which exceeded
> specs until they got transferred to another fab. Afterwards, the part
> still met their specs, but didn't meet the customers requirements. Of
> course the manufacturer put in some effort trying to make the device
> as good as it was because it was a good customer, but there's only so
> much effort you can justify for 100k parts a year. For small-value
> varicaps, where you can dice easily 30k-50k pieces out of a single
> wafer, the customer would happily have bought a full manufacturing lot
> had they known before the fact.
> 
>>> Like all those microwave MMICs with low noise, they worry about 100
>>> MHz and up (if not 1GHz), they certainly don't worry (or control) for
>>> noise at 5 MHz, or where the 1/f knee is. So just because you got 
>>> good
>>> results with a batch of them, the next batch might not.  It's not 
>>> even
>>> clear you could come up with a standardized test method, because the
>>> noise depends on a lot of other factors (drain current, for 
>>> instance).

>> > When it changes from lot to lot, then you have lost. You cannot catch
>> that on the wafer tester. No one can pay for the tester time.
>> A simple BJT or FET circuit is allotted a ms or so in total, maybe.
>> You cannot measure 1/f in the 100 Hz range in that time. The picture
>> of the FET amplifier I had 3 days ago took 35 minutes, per trace.
>> By far, most of the wall time is aquisition time for the lowest 
>> octaves.
>> 
> It depends a bit on the needs. Whether we're talking about DC, analog,
> RF or digital testers for example. But even for the most complex
> tests, tester time is cheap compared to engineering time for test
> setup.

I've worked for a tester manufacturer near Stuttgart for a project, and
their customers had a completely different view about this. :-)

I had a mid-scale mixed signal tester just for myself to exercise my
software; only half a day per week for someone else's regression tests.
In our hall there were 300 engineers, almost entirely for software, only
15 or so for hardware design. A different customer of mine was quite
proud on their E5052B; in the neighbor cubicle someone sent half a dozen
of them one morning to calibration. That did not create any bottleneck.
That all must be paid for. Then you arrive at options: Normal vector
speed is <crawl>. For $$$ you get 10eXYZZY vectors at warp speed. Once.

My VNA cannot handle mixers because of a missing software option. As 
much
as I hate it, I can understand it.


> But of course you're right, as 1/f takes long, one will have to trade
> test time versus lower frequency corner and sample count. Doing full
> manufacturing screening (as in test every single manufactured device)
> is prohibitively costly more or less independent of lower frequency
> corner for all but the most demanding applications. Testing a dozen
> devices out of a full wafer (with, say, 10 k devices per wafer) is
> manageable. Last year I measured a few samples for 1/f down to 0.01
> Hz. That's a matter of starting the measurement on friday afternoon
> and then going home for the weekend. Next sample on the next weekend
> ;-) There was no point in starting the measurement before friday
> afternoon in any case as during the week the environment was more
> noisy than the DUT...

Reminds me of our bit error rate measurements in fiber optics. We had
to make sure, that NOBODY, not even the CEO took his cell phone into the 
lab.

Can you tell us what you used as bias and power supplies for these 0.01 
Hz
measurements? A tiny hint? Please, pretty please?

In Art Of Electronics ed 3 of Hill & Horowitz is a transistor noise
measurement circuit. I have built it, but then featuritis crept in:
NPN, PNP, JFETS, enhancement & depletion, fat decoupling that must
be polarity-switched...
I still have problems / doubts with the bias supply, I must simplify
the entire thing. Maybe I'll make a board layout.

regards, Gerhard.