[time-nuts] Re: GPSDO Control loop autotuning

[Matthias Welwarsky]

On Montag, 11. April 2022 11:15:57 CEST Poul-Henning Kamp wrote:
> --------
> 
> Markus Kleinhenz via time-nuts writes:
> > But I think i got some pointers that can put you on your path.
> 
> One (always?) overlooked metric, is the frequency spectrum of the
> zero-crossings, of the phase difference input to the PLL.
> 
> (NB: This obviously require good resolution of the phase error,
> including application of the "negative sawtooth" correction,
> otherwise the "hanging bridges" noise will swamp the signal
> you are looking for.)
> 
> If your loop is (too) tight, the PLL will chase every wiggle in the
> GPS signal and your phase difference input to the PLL will change
> sign all the time.
> 
> If your loop is (too) loose, the PLL will not follow the GPS signal
> as close as it should, and the phase difference will only rarely
> change sign, if your OCXO/Rb drifts, possibly not ever.

Thing is, as long as your phase error is constant, there's no drift. The 
frequency is still "locked", just the edge of your LO signal is leading or 
lagging the timing reference. It is only if you want to generate a UTC 
synchronized time pulse that this might create a problem (depending on your 
requirements). Anyway a PLL will cause a more or less subtle drift all the 
time as it slowly tries to steer the phase of the LO to towards the time 
pulse. 
 
> My heuristic is that when you plot the histogram of the time between
> zero-crossings, you want the "bulge" on the low side of, but close to,
> the "allan-intercept" (Ie: where the OCXO and GPS allan curves cross.)
> 
> If you are working with 3rd order PLLs (predicting frequency drift),
> plotting separate histograms of the duration of positive and negative
> phase inputs helps:  The more they overlap, the better your drift estimate.

That's an interesting metric, but just as well you could record the phase 
error over a certain time and feed it into a linear regression solver. That'll 
give you the drift in s/s and you want it to be 0 (or, like, close). You'll 
know if your PLL is coupled too loosely if you see a drift.

Or, just look at the ADEV of the phase error. If the curve is going up instead 
of down, you know something's not quite right ;)