[time-nuts] Re: General discussion of PID algorithms applied to GPSDO control loops (continued 1)

[André Balsa]

Hi Tobias,
There are various approaches to using AI algorithms in PID controllers. One
approach (which is even described in a YouTube video) is to use genetic
algorithms to find optimal (or more precisely, near-optimal) coefficients
for the PID controller. However, that is not the approach I want to try to
use for the STM32 GPSDO.
I intend to use this Arduino library:
https://github.com/GiorgosXou/NeuralNetworks
and have the NN "learn" to control Vctl.
Whether it succeeds or not, it should be interesting to watch a machine
learning algorithm at work in the control loop of a 100% Open Source 40€
DIY GPSDO that can be put together on a breadboard in one afternoon!

On Mon, Apr 18, 2022 at 12:11 AM Pluess, Tobias via time-nuts <
time-nuts at lists.febo.com> wrote:

> Hi André,
> possibly you should also consider contributing to the Kalman filter
> approach; I haven't read your entire thread yet, but I would be interested
> in filtering the TIC readings with a Kalman filter, using the Kalman filter
> as a kind of observer, and feeding the filtered output to the PID
> controller.
> In my opinion, this approach is missing in your list ;-)
> the neural network is of course the really crazy stuff, do you have some
> literature about that? So would you use the NN also to filter the TIC
> readings and then provide filtered readings to the PID, or is your approach
> a totally different one?
>
> anyways, as glen eglish said:
> "fantastic discussion going on here. love it."
>
> best
> Tobias
> HB9FSX
>
>
>
> On Sun, Apr 17, 2022 at 6:55 PM André Balsa <andrebalsa at gmail.com> wrote:
>
> > Hello Poul-Henning,
> > First let me thank you for your career-long significant contributions to
> > the Open Source world and to global internet standards.
> > Second, regarding your comment that "You _can_ have hybrid steering, but
> > you must assign "weight" to the
> > different contributions, so that they will never oscillate."
> > That is exactly how I intend to implement the hybrid PLL/FLL control loop
> > for the STM32 GPSDO. By December this year I should have implemented
> > separate PLL, FLL and hybrid PLL+FLL PID control loops for my STM32 GPSDO
> > project and hopefully I'll be able to collect enough data to compare
> their
> > behavior. I would also like to try programming a Neural Network (NN)
> based
> > GPSDO control loop algorithm and again compare its behavior with the
> > "classic" PID control loops.
> > Many thanks for your comment,
> > Andrew
> >
> > On Sat, Apr 16, 2022 at 4:55 PM Poul-Henning Kamp <phk at phk.freebsd.dk>
> > wrote:
> >
> > > --------
> > > Bob kb8tq writes:
> > >
> > > >>> You mean the FLL and PLL are exclusive of each other ? I guess you
> > are
> > > >> right, but I am trying to think "outside the box" and see if there
> are
> > > any
> > > >> alternatives.
> > > >
> > > >You will have two people driving the car at the same time. One hits
> the
> > > >accelerator and the other hits the brakes at the same time. They both
> > > can’t
> > > >be active *and* feed the EFC at the same time. The practical answer is
> > to
> > > >run each during the warmup phase that it makes sense to do so.
> > >
> > > You _can_ have hybrid steering, but you must assign "weight" to the
> > > different contributions, so that they will never oscillate.  I normally
> > > have found it better to have a big switch which decides who gets to
> > > control,
> > > based on the (external) circumstances.
> > >
> > > As a general rule of thumb, FLL's only make sense if the product
> > > of the rate at which you measure phase difference, and the jitter-noise
> > > when you do, ends up way to the right and above the allan-intercept.
> > >
> > > Prof. Dave's infamous "Call NIST once a day with a modem" mode in
> > > NTPD is a good example:  Forget about tracking temperature, XO drift
> > > or anything else:  Just try to get the average frequency right on a
> > > timescale measured in weeks.
> > >
> > > Poul-Henning
> > >
> > > PS: When you implement your PLL:  The way to void "wind-up"
> > > durign startup, is to short the integrator, until the phase error
> > > has reached its proper sign.  It is surprising how hard it is
> > > to write code to spot that, compared to deciding it manually :-)
> > >
> > > --
> > > Poul-Henning Kamp       | UNIX since Zilog Zeus 3.20
> > > phk at FreeBSD.ORG         | TCP/IP since RFC 956
> > > FreeBSD committer       | BSD since 4.3-tahoe
> > > Never attribute to malice what can adequately be explained by
> > incompetence.
> > > _______________________________________________
> > > time-nuts mailing list -- time-nuts at lists.febo.com -- To unsubscribe
> > send
> > > an email to time-nuts-leave at lists.febo.com
> > > To unsubscribe, go to and follow the instructions there.
> > _______________________________________________
> > time-nuts mailing list -- time-nuts at lists.febo.com -- To unsubscribe
> send
> > an email to time-nuts-leave at lists.febo.com
> > To unsubscribe, go to and follow the instructions there.
> _______________________________________________
> time-nuts mailing list -- time-nuts at lists.febo.com -- To unsubscribe send
> an email to time-nuts-leave at lists.febo.com
> To unsubscribe, go to and follow the instructions there.