[time-nuts] Symmetricom/Datum FTS-1050A Disciplined Frequency Standard

[Joseph Gwinn]

On Wed, 06 Apr 2022 03:30:35 -0400, time-nuts-request at lists.febo.com 
wrote:
time-nuts Digest, Vol 216, Issue 10

>>> 
>>> Message: 4
>>> Date: Sun, 3 Apr 2022 09:53:18 -0400
>>> From: Bob kb8tq <kb8tq at n1k.org>
>>> Subject: [time-nuts] Re: Low Phase Noise 10 MHz bench signal source
>>> 	sought
>>> To: ew <ewkehren at aol.com>, Discussion of precise time and frequency
>>> 	measurement <time-nuts at lists.febo.com>
>>> Message-ID: <11376923-062A-4011-A6D4-1D9CE3361466 at n1k.org>
>>> Content-Type: text/plain;       charset=utf-8
>>> 
>>> Hi
>>> 
>>> These days a PLL is going to either be analog or digital. If it’s 
>>> analog, you get into size constraints related to capacitors
>>> as you go to lower crossover frequencies. With digital, you
>>> get into all of the noise issues that any digital circuit will have.
>>> (Yes, they can be addressed but it’s not easy at very low
>>> offset frequencies). 
>> 
>> All of the loop filters I've seen recently had nominal bandwidths in 
>> the Hertz 
>> to tens of Hertz, usually implemented in some kind of digital signal 
>> processor.  
> 
> 10 Hz or higher is certainly do-able with analog loop components. 
> There are a lot of products out there that work that way.
> 
>> 
>> About 30 years ago, there was a legacy 5 MHz disciplined 
>> oscillator that could be set to a 100-second response time.  I never 
>> did find any real technical data or patents on it.  I don't recall 
>> its name, but it may come back to me.  I think it was made by 
>> Symmetricom.

I finally recalled the details, after all these years.  It was from 
Symmetricom, they having acquired Datum in 2002.  It was model 
FTS-1050A Disciplined Frequency Standard.  Despite the implication of 
the product name, it does appear to be a phase-lock loop design at 
heart, from the users manual (my copy being dated 1999).  This is the 
one that I suspect was in fact a 3rd-order PLL design, because it 
would become unstable if the the incoming reference were too faint, 
being far more fussy than your usual PLL, which would happily lock 
onto a pretty faint and ratty reference signal.

It has two switch-selectable integration periods, one second and one 
hundred seconds.  I assume that the integration is digital, but in 
hardware versus a computer.

I can provide the documentation, if anybody wants a copy.  Apparently 
a number of folk were looking here, over the years.  Maybe something 
to add to Febo.com.

I wonder who the designers were.  Hmm.  I bet that Robert Lutwak, 
William Riley, and Kenneth Lyon were involved, as these folk are the 
inventors of patents assigned to DATUM TIMING TEST AND MEASUREMENT 
Inc and Datum Inc in the day.  I worked with Ken Lyon some time ago, 
if I have the right Ken Lyon.


Joe Gwinn