[time-nuts] Re: RCB-F9T Adapter PCB with USB and 50 Ohm Timepulse SMA Connectors

[Bruce Griffiths]

I don't see any explicit jitter specs on the BUF602 datasheet either.
Have you measured it?
How consistent is it from part to part?
The jitter of most CMOS families has been measured.
For example 74HC buffers typically have ~4ps jitter at room temperature.
Even this is much lower than the jitter of typical FPGAs when the effect of cross coupling from other clock domains such as internal oscillators etc are taken into account.
Faster logic families such as 74AC buffers (~ 1ps) have even lower jitter.
CMOS devices have a typical propagation delay tempco of around 0.4% of the delay per/C. FPGA gates have similar delay tempcos.
Neither the delay tempco nor the jitter is typically specified on CMOS device datasheets nor are they on the BUF602 datasheet so you have to measure them or leverage the results obtained by others.

 
Bruce  

> On 24/08/2022 19:19 Carsten Andrich via time-nuts <time-nuts at lists.febo.com> wrote:
> 
>  
> Hi Bob,
> 
> On 24.08.22 04:20, Bob kb8tq wrote:
> > The BUF 602 needs dual 5V supplies to hit 3.3V logic levels. Running multiple supplies is a
> > bit of a PIA. Since this*is*  a logic signal, cheap / fast / stable logic gates would seem to be
> > the obvious way to get the job done. 3.3V supply and away you go … The usual suspects
> > are all at least as fast and at least as low jitter as the BUF 602.
> >
> > Bob
> 
> I initially thought the same about the dual supplies. Fortunately, the 
> required average currents are fairly low (<100 mA to drive 5 loads at 
> 3.3V and 50 Ohm each), so an inverting charge pump will do the job. The 
> SOT-23 LM2776 requires 3 capacitors in external circuitry, the WSON 
> LM27761 needs 4 caps and 2 resistors. I'm using the LM27761 on my 
> RCB-F9T adapter board. See my initial post for the layout.
> 
> Can you point me to any measurements or data sheets that characterize 
> the rise time, temperature dependency, and/or jitter/phase noise 
> performance of suitable logic gates? The fastest device families I could 
> find are 74LVC, 74AVC, and 74AUC. The 74HC often relied upon are 
> actually very slow [1]. I've discussed using 74-type components on the 
> EEVblog forum [2]. The 74s' typically large temperature coefficient 
> alone makes me reluctant to use them. The lack of jitter specs is an 
> exclusion criterion for me.
> 
> What are the "usual suspects" you refer to? I couldn't find any 74ish 
> device with official specs that can compete with the BUF602. As a 
> reasonably linear analog buffer, it shouldn't add any jitter on top of 
> its input voltage noise and has >45 dB PSRR up to 1 MHz. Its 8 V/ns slew 
> rate enables <0.5 ns rise times and it is straightforward to achieve 50 
> Ohm source termination. Improper source termination is also an exclusion 
> criterion for me.
> 
> In comparison, logic gates don't spec rise times <1 ns, have presumably 
> – correct me if I'm wrong – negligible PSRR, don't specify output 
> impedance, and require paralleling multiple outputs to drive 50 Ohm loads.
> 
> While the use of 74s may work for my application (whether sub-optimal or 
> not would be subject to tests), I'd rather err on the side of caution by 
> using parts that are explicitly specified for my use case.
> 
> Best regards,
> Carsten
> 
> P.S.: If you're wondering why I need such high slew rates, my 
> application is phase synchronization of RF synthesizers like TI's 
> LMX2594. These require low phase noise, high slew rate reference and 
> sync signals. Again, I prefer to err on the side of caution by providing 
> the highest slew rate I can realize with reasonable effort.
> 
> [1] https://www.ti.com/lit/sg/sdyu001ab/sdyu001ab.pdf#page=2
> [2] 
> https://www.eevblog.com/forum/projects/gpsdognssdo-stm32g4-u-blox-zed-f9t-tdc7200/msg4357849/#msg4357849
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