[time-nuts] Re: PLL subharmonic spurs

[Attila Kinali]

On Mon, 7 Feb 2022 09:51:27 +1100
glen english LIST <glenlist at cortexrf.com.au> wrote:

> If you are interested in harmonics of the reference frequency at the 
> input to the phase detector, this will be entirely defined by the 
> fourier series of the source. Get yourself a 2nd year EE student, 
> they'll have this info for you.

I do not think that this tone is warranted here.

First of all, nothing about PLL is trivial. Especially not their
non-linear and non-ideal behaviour. I know many EEs who do not fully
understand these, much less have mastered them. Heck, I barely understand
these and I am considered the local PLL-"expert" where I am.
And it gets only worse the more closely one models the parts of a PLL,
most of which are quite far from their usually modeled ideal behaviour.

Second, keep in mind that many people on the time-nuts mailinglist
are hobbyists who came here through various paths. Very few of
those have the mathematical background to read and understand the
textbooks on PLLs, much less to calculate something that is not
in there. Yes, we have quite a few engineers and scientists with
a very high level here. While I do hold these engineers and scientists
to a higher standard and expect them to write mails according to that
level of knowledge and understading, I do not apply that to the majority
on time-nuts. Especially not someone who is new on the list and whose
background is not known. And neither should you.


But back to the topic at hand....

[1] Gives an easy, though probably not very accurate way how to calculate
some of the spurs caused by current leakage.

A more complete analysis, can be found in [2].

For general discussion about PLLs and their behaviour, I would recommend
Best's book [3] (which OP already has) and Gardner [4]. The latter is
quite a bit more theoretical and more complete in its treatment of
PLL behaviour, but also quite a bit harder to apply to a design.

Another book that I quite recommend is [5], written by a TI engineer,
which focuses on the practical aspects of discrete PLL circuit design
and the difficulties faced there. It contains some discussion of spurs,
but I don't remember whether it had a in-depth discussion of the
reference spurs.

Sorry that I can't give a more to the point answer. I haven't looked
into the the spur behaviour of PLL yet and thus have only the most
basic knowlege about it.

			Attila Kinali


[1] "A Simple Method to Accurately Predict PLL Reference Spur Levels
Due to Leakage Current", by Azarian and Ezell, Linear Application Note 143,
2013
https://www.analog.com/media/en/technical-documentation/application-notes/an143f.pdf

[2] "Causes of PLL spurs and their modeling", by Biswas and Bhattacharyya,
2019
https://doi.org/10.1007/s10470-019-01477-z

[3] "Phase-Locked Loops - Design, Simulation and Applications", 
by Roland Best, 5th edition 2003

[4] "Phaselock Techniques" by Floyd Gardner, 3rd edition, 2005

[5] "PLL Performance, Simulation, and Design", by Dean Banerjee,
5th edition, 2017
http://www.ti.com/lit/ug/snaa106c/snaa106c.pdf
-- 
The driving force behind research is the question: "Why?"
There are things we don't understand and things we always 
wonder about. And that's why we do research.
		-- Kobayashi Makoto