[time-nuts] Re: PLL subharmonic spurs

[Bob kb8tq]

Hi

On a lot of PLL’s noise is as much an issue as discrete spikes 
( = spurs ). If one widens the definition out to include noise then
things get even more complicated. 

Simulation !!! There are free programs out there and “pay” stuff
as well. If you are starting from scratch, they likely will catch a
lot of things you would have missed. 

Bob

> On Feb 7, 2022, at 10:29 AM, Lux, Jim <jim at luxfamily.com> wrote:
> 
> On 2/7/22 6:05 AM, Attila Kinali wrote:
>> On Mon, 7 Feb 2022 09:51:27 +1100
>> glen english LIST <glenlist at cortexrf.com.au> wrote:
>> 
>>> If you are interested in harmonics of the reference frequency at the
>>> input to the phase detector, this will be entirely defined by the
>>> fourier series of the source. Get yourself a 2nd year EE student,
>>> they'll have this info for you.
>> I do not think that this tone is warranted here.
>> 
>> First of all, nothing about PLL is trivial. Especially not their
>> non-linear and non-ideal behaviour. I know many EEs who do not fully
>> understand these, much less have mastered them. Heck, I barely understand
>> these and I am considered the local PLL-"expert" where I am.
>> And it gets only worse the more closely one models the parts of a PLL,
>> most of which are quite far from their usually modeled ideal behaviour.
> 
> 
> This is very true. At some trivial level, the output of the phase detector is some sort of variable duty cycle square wave feeding into a low pass filter, so a combination of the theoretical spectrum of edges passed through the filter would get you started.  In any case, it would tell you where the spurs are likely to be.
> 
> However, real PLLs often have other (non-idealized) waveforms going into the loop filter. A lot have little pulses (charge pump designs), but the pulses change their size and shape depending on how the PLL is programmed.  There's also interesting effects if the inputs to the phase (or phase frequency) detector have harmonic content, or spurious from other places. It wasn't a PLL, but an ADC, where I had a problem with the CPU clock rate (at 66 MHz) leaking in to either the power or the clock a ADC running at a sampling rate of 50MHz. There's a nonlinear sampling process (just like in a PLL), and small changes in the sampling instant cause spurs.
> 
> Even harder is figuring out what the spur *output* looks like from the PLL.  You may have figured out how the spurs look coming out of the loop filter, but then, that goes into the VCO, and VCOs are hardly paragons of perfectly linear behavior - they have their own control voltage time and frequency domain behavior.
> 
> to summarize, I think you can get "close" to a decent prediction if you're using a well known PLL part in a well understood area of operation. Other than that, you'd best contemplate building a breadboard or prototype and changing it.  I've got some experience making 7 and 8 GHz signals with the ADF4360, and there are dozens of parameters that can be adjusted, the results of which are not trivially predictable.  In our application, we needed to tune a 100 MHz range, and have manageable spur levels to meet the NTIA/SFCG masks (which are generally -60dBc far out).
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