[time-nuts] Re: DIY Low offset Phase Noise Analyzer (Erik Kaashoek)

[Magnus Danielson]

Erik,

On 7/9/22 22:06, Erik Kaashoek via time-nuts wrote:
> Getting the simple PNA to lock was a bit difficult due to the overly
> simplistic translation of the mixer output to the Vtune of the OCXO
> To get some more flexibility I added a summing opamp that summed the mixer
> output with the output of the coarse tuning potmeter. As the summing causes
> inversion one extra inverting opamp was added. This made the loop gain
> constant
> To ensure the mixer is in quadrature another opamp was added that amplified
> the mixer output into two LEDs. One LED on when below zero ouput from
> mixer, the other on when above zero and both dim when zero output. This
> made tuning the coarse frequency simple. Turn till the blinking stops and
> both LED's light up dim. The fine frequency potmeter was no longer needed
> and the frequency counter is also no longer needed to get into lock
> With the summing opamp it is also possible to add an integrator but this
> has not been done yet.

So, this is where you should attempt the PI loop.

In theory, you have one proportional path P and one integrating path I 
that sums to form the EFC. You can imagine this as two op-amps having 
inverted gain and then a summing amp to sum these two up. Thus, you have 
for the P path a resistor in the negative feedback path and for the I 
path a capacitor in the negative feedback path.

Such a setup is nice for testing, but a bit excessive as one progresses. 
One can actually reduce this to a single op-amp with the resistor and 
capacitor of the negative feedback to be in series, having a common 
input resistor.

The integrator part will hold the state that ends up being the DC part 
of EFC. The proportional path will provide the AC path and set the 
damping factor for the PLL, you want it well damped.

This would replace your normal loop filter. You would still want a 
filter to reject the sum-frequency out of the mixer.

The P gain is proportional to the PLL bandwidth time damping factor.

The I gain is proportional to the PLL bandwidth squared.

The capture range is for all practical purposes infiinte (it's wide 
enough). The capture time depends to the cube on the PLL bandwidth, so 
altering the PLL bandwidth between unlocked and locked conditions have 
proven very useful approach to speed things up if one has a need for 
larger lock-in frequencies. Rough-tuning with a trimmer can reduce it 
significantly. The lock-detection is very simple detection of the 
presence of beat-notes or not, that AC component dies away as it locks.

Anyway, the benefit of the PI loop filter is that you can be rather 
brutal with parameters, it will lock. So, it can be worth experimenting 
with it. I've found that one can ball-park things fairly quickly knowing 
how to change the P and I for wished PLL bandwidth and damping. Very 
experimentally friendly.

I should advice you that any PLL will provide a low-pass filter of the 
reference input, and a high-pass filter on the noise inside the loop, 
which includes that of the oscillator. This can help you identify likely 
sources of disturbances as per their frequency in relation to the PLL 
loop bandwidth.

Cheers,
Magnus

> Shielding is now the biggest problem as any nearby coax connected to a
> 10MHz source will cause a huge amount of spurs when not at exactly the same
> 10MHz
> Ultra low noise opamps have been ordered to hopefully reduce the internal
> noise of the PNA but the reference OCXO may already be the limiting factor.
> The REF voltage output of the OCXO turned out to be rather clean. Much
> cleaner than a 8705 voltage regulator
> Erik
> _______________________________________________
> time-nuts mailing list -- time-nuts at lists.febo.com
> To unsubscribe send an email to time-nuts-leave at lists.febo.com