[time-nuts] Re: Network interface cards that support timestamping

[Gabs Ricalde]

On Tue, Jan 31, 2023 at 8:58 PM Hal Murray via time-nuts
<time-nuts at lists.febo.com> wrote:
>
> I've daydreamed about an FPGA with a clock input from your best house clock.
> The idea is that you program it to keep POSIX time: seconds and nanoseconds
> and set things up so that  users can map it into memory read-only.  All you
> have to do to get the time is read a 64 bit register from a device.  Extra
> credit if you have PPS inputs that capture a time stamp etc.
>
> Anybody know how long it takes to read a device register?
>

I tried interfacing a cheap FPGA board (QMTECH XC6SLX16) with the LPC
bus, accessible via the TPM header on some motherboards. Reading 1
byte takes around 1.5 us, and then you can read the rest of the
counter.

The rest of this project has an OCXO, a PPS timestamping counter at
slightly less than 1 GHz using the Spartan 6 ISERDES, and a Linux PTP
hardware clock (PHC) driver (just the clock without the networking
parts). Instead of directly using the PHC, chrony can tightly sync the
system clock (TSC) from the PPS timestamped by the PHC (the PHC itself
may be free running). I may revisit this project and provide
details/measurements if anyone is interested.