[time-nuts] Re: Can Anyone Help Me Get PPS Into This Mini PC?

Ed Marciniak ed at nb0m.org
Thu Feb 15 16:52:48 UTC 2024


The raspberry pi 5 moved the GPIO to a PCIe device with its own AXI bus, rather than an AXI bus on the CPU/GPU die.

If the bus were busy and happened to send maximum 256 byte data blocks, it could add not insignificant latency.

I recall seeing something about the Ethernet having IEEE-1588 on the PI 5


Here's something about the pi compute module 4 and PTP (spoiler, you get a 1.8V input or output pin but not both on the CM4 official IO board). The compute module 4 has a different Ethernet chip than the full size pi 4, which lacks 1588 support. The datasheet conflicts in suggesting the IO is 3.3V. I don't profess to know and haven't measured it myself.

https://www.jeffgeerling.com/blog/2022/ptp-and-ieee-1588-hardware-timestamping-on-raspberry-pi-cm4

Given what the CM4 modules and an IO board cost ($65 and up total), something that is potentially accurate to under 20ns is impressive. I wouldn't even try to use an older or other pi as a solution.

________________________________
From: Michael Wouters via time-nuts <time-nuts at lists.febo.com>
Sent: Wednesday, February 14, 2024 3:59:13 PM
To: Discussion of precise time and frequency measurement <time-nuts at lists.febo.com>
Cc: Michael Wouters <michaeljwouters at gmail.com>
Subject: [time-nuts] Re: Can Anyone Help Me Get PPS Into This Mini PC?

Hello,

Adding to Achim’s comments, I have used similar GPIO ports on some small,
Intel-based SBCs. These are associated with the 8186x family of I/0 chips
which provide a parallel port, UARTS, floppy controller etc. Fintek is one
manufacturer. These can only be used as a simple digital port that can be
written to and read from user space.

My recent experience with PPS timestamping on Intel is that it does not
work so great anymore. The serial port option for low latency interrupt
servicing no longer does anything. I see regular 100 microsecond spikes in
timestamping which hose any attempt to keep precise time. So RPi is what I
use now.

Cheers
Michael


On Thu, 15 Feb 2024 at 4:57 am, ASSI via time-nuts <time-nuts at lists.febo.com>
wrote:

> On Freitag, 9. Februar 2024 23:10:26 CET Ed Armstrong wrote:
> > If any of you follow my
> > first link, you will see the little mini PC has a header for GPIO. It is
> > a 2x5 header with I believe a 2 mm pitch. According to the listing,
> > there are four input and four output pins. I assume the other two pins
> > are either both grounds or both positive, not really sure.
>
> This arrangement indicates most likely a separate GPIO expander chip that
> is
> connected to some internal SPI or LPC bus and mapped to an 8bit
> "register".
> These are probably not suitable for PPS the same way as the GPIO on RasPi
> and
> may even need to get polled.  However, it is _possible_ that the header
> provides access to some PCH GPIO pins, which would in principle enable the
> use
> of PCH timestamping on two of these pins unless they're already used up
> elsewhere.
>
> > Now comes my question. Can any of you tell me how to use these GPIO
> > pins? I can find tons of information very easily on setting this thing
> > up as a router, NAS, or as a desktop computer. I have not been able to
> > find a single post related to those GPIO pins. I can't find the pin out,
> > can't find out what voltage they are supposed to work at, nor any
> > information about communicating with them in Linux. I queried the
> > system, hoping I could look up the motherboard online, and this is what
> […]
> > I also tried dmidecode -t baseboard, this obviously gave more details,
> > but most devices were just listed as "other". I haven't found this to be
> > terribly useful.
>
> If the system is correctly recognizing the GPIO resources, they should
> show up
> under /sys/class/gpio and link to the actual devices which should give you
> a
> clue as to what actual chips are behind it.  Some of the PCH GPIO will be
> used
> internally (for instance the i226V needs at least one GPIO for power
> gating)
> and therefore may be not get exposed.
>
>
> Regards,
> Achim.
> --
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