[volt-nuts] 32-Bit PWM divider

Mon Oct 4 18:43:09 UTC 2010

Andreas

There is an large error in the resistor values that determine the gain 
of the LS PWM DAC in the EDN article resulting in a gain mismatch 
between the most significant 16 bit PWM DAC and the least significant 
PWM DAC.
The resultant linearity error is much larger than the effect of the 
difference between the 5 ohms and the 7.15 ohms you used.
This gain mismatch will result in the ~ 16 bit nonlinearity error that 
you observed.

Bruce

Ulrich Bangert wrote:
> Hello Andreas,
>
> when I came over this circuit I was in search for a 24 Bit DAC for the EFC
> of an OCXO. For hat reason everything was a bit less ambitious than you are
> in search for. The reference I used was a LT1021, much inferior than the
> LTZ1000 in terms of tempco but no problem for this application because its
> use inside a closed regulation loop. The resistor networks were computed
> new, so i have no experience with it's original values.
>
> The noise measurements that I made were done with a HP3457 in
> "high-resolution" mode (7-1/2 digits). The HP3457 was set to integrate over
> 50 power line cycles. If I remember correct the noise that i measured was
> pretty much that of the reference divided down according to the pwm ratio.
>
> Best regards
> Ulrich Bangert
>
>    
>> -----Ursprungliche Nachricht-----
>> Von: volt-nuts-bounces at febo.com
>> [mailto:volt-nuts-bounces at febo.com] Im Auftrag von Andreas Jahn
>> Gesendet: Sonntag, 3. Oktober 2010 23:11
>> An: Discussion of precise voltage measurement
>> Betreff: [volt-nuts] 32-Bit PWM divider
>>
>>
>> On April, 24th Ulrich Bangert wrote:
>>
>>      
>>> while I have no experience at all with the AD5791 I would
>>>        
>> like to draw
>>      
>>> your attention to the fact that even higher reolution monotonic DACs
>>> are easily constructed from "normal" microcontroller's PWM outputs.
>>> Well, of course you need some additional electronics like in
>>>        
>>      
>>> http://www.electronicsweekly.com/Articles/2008/10/30/44817/dc
>>>        
>> -accurate-
>>      
>>> 32-bit-dac-achieves-32-bit-resolution.htm
>>>        
>>      
>>> but this stuff really works!
>>>        
>> I have built the cirquit from EDN (with some modifications)
>> which seems to
>> be the same that Ulrich used:
>> http://www.edn.com/article/471981-DC_accurate_32_bit_DAC_achie
>> ves_32_bit_resolution.php
>>
>> but the values that are stated in the article are far beyond
>> that what I
>> have measured.
>>
>> My modifications are: using MAX6250A instead of AD586L.
>> R2,R3 = 51R and R6 = 0R so that I get around 30 Bits
>> resolution with 2 Bits
>> overlap.
>> C1 = 100nF , R1 = 100K with 100 Hz period. (I tried 244 Hz
>> period with R1 =
>> 41K but this has nearly no impact)
>> All built on a soldered breadboard using star grounding.
>>
>> The issues that I have with the cirquit are:
>>
>> 1. the given formula for output voltage is not correct. When
>> recalculating I
>> get 50% from VRef at PWMH = 8000 and PWML = 8000 since the
>> voltages are not
>> added. They are mixed in relation to the resistor values. The
>> maximum output
>> voltage one can get is 65535/65536 * VRef.
>>
>> 2. Linearity: With the original 5 Ohms Resistor I measured
>> around 60-65uV
>> maximum linearity deviation at 2.5V Output. This would give
>> about 16 Bits
>> Linearity in my case. Carefully adjusting R7 to linearity
>> (7.18 Ohms) gives
>> around 12-15uV (3ppm) linearity. But this is far from the 22
>> bits = 0.3 ppm
>> linearity stated in the article. The linearity curve is
>> relative flat up to
>> 75-80% of the range. Above 80% the linearity error increases
>> continously.
>>
>> 3. settling time: Although having carefully adapted the
>> integration time
>> constant to the period time the output gets only 80-90% of
>> the voltage step
>> in the first step. When looking at the oscilloscope the
>> integrator output
>> breakes down at the time when S3 switches. So it needs around
>> 5 PWM cycles
>> to settle on the scope.
>>
>> 4. Large current spikes through S3: At 2.5V Output the
>> integration capacitor
>> will have 2.5Vpp Integration ripple. When having a 50% duty
>> cycle for S3
>> there will be current spikes of 2.5V limited only by the 200R
>> resistor and
>> the resistance of the switch. These spikes increase the
>> output noise. (I
>> measured around 100uVpp with a LTC2400 A/D-Converter).
>> Increasing the PWM
>> duty cycle to around 97% will give a good compromize between
>> noise and
>> settling time of the output capacitors.
>>
>> 5. large negative output spikes on voltage steps>= around 0.5V: When
>> switching between 2 PWM duty cycle values I see large
>> negative spikes (up to
>> negative voltages) on the output voltage. For me it seems
>> that the input
>> protection diodes between negative and positive input (1.1V
>> forward voltage)
>> are going to be forward biased.
>>
>> 6. Output noise measured with a bandwidth limited fourth
>> order (0.1Hz to 10
>> Hz) amplifier (10000 fold) shows 10-15uVpp "noise". This noise is not
>> randomly distributed but shows some cyclical staircased
>> behaviour. The 100nF capacitor for the first integrator is a
>> polypropylene type. The
>> two 1uF capacitors are still mylar type. Perhaps the "staircase" has
>> something to do with dielectric absorption.
>>
>> Has anybody any idea how to get better results from this
>> cirquit? Anyone
>> else who built this cirquit?
>>
>> @Ulrich: how did you get your good results from noise
>> measuring (only the
>> LTZ1021 noise = 3uVpp)
>>      Which capacitor types did you use? mylar or polypropylene or else?
>>       Any hints on the building of the cirquit?
>>
>> best regards
>>
>> Andreas
>>
>>
>>
>>
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