[volt-nuts] Voltage divider
Jan Fredriksson
jan at 41hz.com
Wed Jan 8 17:29:47 EST 2014
JD,
Thanks for giving input on this. But I will need a pointer on how to decode
your figures :-;
I am not concerned about resolution as much as predictable output, be
it linear or other transfer function. MOS devises will have turn-on/off
delays, rise/fall times etc that mess things up. Enen linear components
like caps and inductors are most likely non-linear at this level. So maybe
a DAC is more straight forward after all.
But perhaps a bit early to go into that. I´m not setteling for a solution
till I have dug into this for a month or two and have more knowledge to
form an opinion.
On Wed, Jan 8, 2014 at 6:00 PM, <volt-nuts-request at febo.com> wrote:
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> Today's Topics:
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> 1. Re: PWM voltage divider (John Devereux)
> 2. Re: PWM voltage divider / now "Voltage divider" (Jan Fredriksson)
>
>
> ----------------------------------------------------------------------
>
> Message: 1
> Date: Wed, 08 Jan 2014 13:53:02 +0000
> From: John Devereux <john at devereux.me.uk>
> To: volt-nuts at febo.com
> Subject: Re: [volt-nuts] PWM voltage divider
> Message-ID: <87y52qy401.fsf at devereux.me.uk>
> Content-Type: text/plain
>
> Jan Fredriksson <jan at 41hz.com> writes:
>
> > I'm thinking of using a PWM divider for voltage generation of adjustable
> DC
> > voltages from a voltage reference.
> >
> > Does anyone have any pointers to circuits, solutions, topologies, error
> > analysis etc. for such solutions?
>
> Hi Jan,
>
> There was a nice thread on sci.electronics.design "SMD TC??" about this.
>
> <
> https://groups.google.com/forum/#!searchin/sci.electronics.design/SMD$20TC$3F$3F
> >
>
> There were interesting ideas in there if you browse through the thread.
>
> Some highlights quoted below, all due to James Arthur I think:
>
> ======================================================================
>
>
> Here's the basic PWM:
>
> .........................
> :
> Vref >----/\/\/-----O :
> R1 \ : R3
> \ : 1M
> O-----/\/\/---+-----> Vout
> : |
> R2 : --- Cf
> 0 >----/\/\/-----O : ---
> : |
> ........................: |
> ===
> Fig. 1
>
> To me, 16 bits on the cheap is plenty cool. But if the bar is doing
> something extraordinary, like 1ppm, then it seems fair to use fancier
> parts.
>
> So, let's assume an FPGA and 100MHz clock rate, driving the switch.
> The switch can either be the FPGA output, or an extra gate (or
> paralleled gates).
>
> We can get 1ppm modulating 100Hz in 10nS chunks. Or 40Hz in 25nS
> chunks, etc. Whatever works out with our switch-speed.
>
> Switch mis-match (R1-R2) produces a code-related error, maximized at
> mid-scale. With R3=1M, my algebra says <0.5ppm non-linearity from
> switch mis-match requires |R1-R2| <= 1 ohm. Y(A)MV.
>
> Paralled gates, analog switches, or a BSS138 buffer stage could do
> that. I measured (characterized) some 74ACxx parts a ways back for
> this.
>
> Another, liberating possibility is to bootstrap the switches,
> canceling most of their effective resistance:
>
> Vcomp >-------------.
> |
> |
> ......................... .-.
> : | | R4
> Vref >----/\/\/-----O : | |
> R1 \ : '-'
> \ : | R3
> O----+--/\/\/---+-----> Vout
> : |
> R2 : --- Cf
> 0 >----/\/\/-----O : ---
> : |
> ........................: |
> ===
> Fig. 2
>
> If Vcomp is such that i(R4) = i(R3), the voltage drops (errors) across
> R1 and R2 disappear. This next version does that.
>
> C1
> Vpwm >-----+----||----.
> .-. .-. | |
> _| |__| |_ =2Vrefp-p| |
> | .-.
> .....................V... | | R4
> : . : | | 100K, 1%
> Vref >----/\/\/-----O . : '-'
> R1 : \ : | R3
> : \ : | 100K, 1%
> : O---------+---/\/\/---+-----> Vout
> : : |
> R2 : : --- Cf
> 0V >----/\/\/-----O : R4=R3 ---
> : : |
> .................:......: |
> ===
> Fig. 3
>
> C1-R4 re-create the same currents as flow in R3. Effective switch
> resistance (R1, R2) is lowered by about two orders of magnitude,
> allowing us to reduce R3 and lower the output impedance.
>
> Filtering the 100Hz PWM to 1ppm takes 14 time-constants = 140mS.
>
> So, Fig. 3 is a working solution. It's linear and accurate, but needs
> a hi-z buffer amp and it's slow. A 16-bit version could be faster,
> with lower-z output. Or, splitting the DAC up into two sections
> improves both those properties too.
>
> C1
> Vpwm(hi) >------------+---||---.
> .-. .-. | |
> _| |__| |_ =2Vrefp-p| |
> | |
> .....................V... .-.
> : . : | | R4
> Vref >----/\/\/-----O . : | |
> R1 : \ : '-'
> : \ : | R3, 0.05%
> : O-------+--/\/\/---+---/\/\/--+-----> Vout
> : : | Rf |
> R2 : : | --- Cf
> 0V >----/\/\/-----O : R4=R3 | ---
> : : | |
> .................:......: | |
> | ===
> |
> |
> Vpwm(lo) >------------. |
> | |
> | |
> .....................V... .-.
> : . : | | R7
> Vref >----/\/\/-----O . : | | = 1000 x R3, 0.05%
> R5 : \ : '-'
> : \ : |
> : O------------------'
> : :
> R6 : :
> 0V >----/\/\/-----O :
> : :
> .................:......:
>
> Fig. 4
>
> If the upper and lower DACS cover 1,000:1 each, we could lower the
> clock frequency to, say, 10MHz, pump it with a uC, and still have a
> 10kHz composite waveform that one-pole-filters to 1ppm in 14 * 100uS =
> 1.4mS.
>
> The R7-R3 ratio is critical to absolute accuracy and monotonicity.
> The top DAC divides Vref accurately into 1,000 parts, so a 1% error in
> the R7-R3 divider ratio represents an error of 1 part in 100 of
> 1/1,000th, or 1 part in 100,000 overall. 0.05% ensures 0.5ppm.
>
> Likewise, to ensure monotonicity to 1ppm, the lower DAC's contribution
> of 1,000 lsb's cannot be off by >1 part (lsb) in those 1,000 lsb's, or
> 0.1%
>
> The low DAC represents a small, code-related d.c. load on R1, R2 via
> R7. That needs to be either kept small, or compensated.
>
> Back to the topic of this thread, the effect of T/C errors in the
> divider resistors is reduced by the divider ratio, a factor of 1,000.
>
> So, there's a stable, accurate, 1ppm PWM DAC made with non-critical
> parts.
>
>
> (more...)
>
>
> >
> > |<--- t(code) ---->|
> >
> > tr h tf
> > |<--->|____________|<--->| _ Vh
> > | /| |\ | /
> > | / | | \ | /
> > | / | | \ | /
> > | / | | \ | l /
> > ....|/ \|______/ ____ Vl
> >
> > |<-----------t(pwm)------------>|
> >
> >
> > Where
> > t(code) is the commanded high time
> > t(pwm) is the pwm period
> >
> >
> > Vh * (t(code) + (tf-tr)/2)
> > V(code) = --------------------------
> > t(pwm)
> >
> > A difference in propagation delay tpd(H->L) - tpd(L->H) has the same
> > effect.
>
>
> >
> > Bootstrapping the output almost eliminates the load on Vref, which
> > effectively kills the Vref ripple current error too. The high DAC
> > timing error effect is still annoying.
> >
>
>
>
> --
>
> John Devereux
>
>
> ------------------------------
>
> Message: 2
> Date: Wed, 8 Jan 2014 17:11:23 +0100
> From: Jan Fredriksson <jan at 41hz.com>
> To: volt-nuts at febo.com
> Subject: Re: [volt-nuts] PWM voltage divider / now "Voltage divider"
> Message-ID:
> <
> CAFoWNwC92SFHPeRu4-vf5heO9_8YWjUsvMgPS6fhVMdUH-AyZQ at mail.gmail.com>
> Content-Type: text/plain; charset=ISO-8859-1
>
> Wow, that triggered a lot of replies, thanks!!!
>
> Now I think I would like to change the subject of the posting to "Voltage
> divider"; what I want to do is generate voltages (from a voltage reference)
> by whatever tecnology is practical. I ruled out resistor divider as to
> complex and then PWM seemed an obvious path as I worked quite a lot with
> switch mode amplifiers. But I will also take a second look at DACs. I
> remember there is an LT? paper on a 20 bit reference DAC solution. This is
> brainstorming time!
>
> So, I got a lot of reading and thinking to do...
>
>
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> End of volt-nuts Digest, Vol 53, Issue 6
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