[volt-nuts] Building a high resolution DAC

[Poul-Henning Kamp]

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In message <20150817151605.6b4150803df29771b9b95ec9 at kinali.ch>, Attila Kinali w
rites:

>I have been pondering how to build a high resolution DAC over the weekend.

I've been looking at the same thing occationally, but every time I
do the math I reach the conclusion that once you get past 18-20
bits things get *really* icky.

I don't see any realistic way to directly go beyond 24 bits which
isn't based on time division rather than unobtainium calibrated
artifacts (resistors/capacitors).  (Read HP's article about the
kelvin-varley-divider they built from calibration-quality resistors...)

On the other hand, it's perfectly possible to get cheap-ish 32 bit
ADCs, which do a pretty good job of not making you laugh.

That points to a hybrid scheme.

Something like 3 twelve-bit DACs cascaded with plenty of overlap,
sampled by a 32 bit ADC, and connected to a sample&hold.

Once the desired value is obtained, switch to sample mode.

As long as you only need slow incremental response from there, you can
leave the Sample&Hold sampling all the time.

Once you get to the end of the lowest DACs range, you need to switch
to Hold until you have your DAC(-lings) into a row again.

I have not tried this yet myself, but once I get down through my
pile of more important projects, but I'll be happy to lend any
assistance I can to the project.



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