[time-nuts] Interfacing a 8dBm sine output of an OCXO to adigital logic standard

[Scott Newell]

At 09:43 AM 9/16/2005 , Poul-Henning Kamp wrote:
>
>In modern computers the synchronous RAM requires clock signals which
>have very tight specs on delay and jitter and the only way this is
>possible in practice is by using 1:1 PLL's as "zero delay buffers".
>
>See for instance:
>
>	http://www.icst.com/datasheets/ics2305.pdf
>
>ICS has many interesting clock chips which can be used for other
>uses than what they were designed.  Worth a browse.

I used one to multiple my 10MHz OCXO reference to 80MHz.  The idea was to
replace the little 80MHz "clock box" oscillator in a Sun IPX with a
precision clock source.  Didn't work.  I guess the IPX doesn't derive its
100Hz ticker from the CPU clock.


--
newell  N5NTL