[time-nuts] Interfacing a 8dBm sine output of an OCXO to adigital logic standard

[Magnus Danielson]

From: "Poul-Henning Kamp" <phk at phk.freebsd.dk>
Subject: Re: [time-nuts] Interfacing a 8dBm sine output of an OCXO to adigital logic standard 
Date: Fri, 16 Sep 2005 17:19:33 +0200
Message-ID: <12012.1126883973 at phk.freebsd.dk>

> In message <MGEKKFGEAIKJOOPJPGIKCEAMFMAA.richard at karlquist.com>, "Richard \(Ric
> k\) Karlquist \(N6RK\)" writes:
> >> 	http://www.icst.com/datasheets/ics2305.pdf
> >> 
> >> ICS has many interesting clock chips which can be used for other
> >> uses than what they were designed.  Worth a browse.
> >> -- 
> >> Poul-Henning Kamp       | UNIX since Zilog Zeus 3.20
> >
> >This chip has 200 ps of jitter!  There is no way you would
> >want to use this with an OCXO.
> 
> Be aware they don't mean the same with "jitter" as you do: they
> include production tolerances, so the 200ps is the worst case jitter
> measured between two output pins on a large lot of chips, not the
> jitter you would measure on a single output on a single chip.

No, it is the jitter of a single output, in a loaded case. It's all in the
JEDEC standard. It should also be noted that it is the cycle-to-cycle jitter,
so triggering at the rising edge of the 66,67 MHz clock what will the jitter
of the rising edge 15 ns (one cycle away) from the trigger point be. These
vendors tend to specify it as "peak-to-peak" where as I tend to use the RMS
measure since if we only see Gaussian phase-noise (actually we are non-Gaussian
but at tau = 15 ns the non-Gaussian noise is well suppressed) and then we can
use the RMS measure, since the peak-to-peak range will expand as we measure a
longer series where as the RMS value stabilizes. It is also good to see if
there is any deterministic jitter component, but if it is a good design there
isn't a trace of one.

The hell with being able to measure jitter easilly is that you get aware just
how bad stuff is all over the place! :P

Cheers,
Magnus