[time-nuts] More on paralleling output gates
John Ackermann N8UR
jra at febo.com
Sun Apr 9 15:20:55 UTC 2006
I screwed up the measurements in the message I just sent. With the room
(and the trace) dimmed for photography, I messed up getting the trace
properly aligned for risetime measurements. I didn't notice until too
late. There won't be a major difference in the results, but I'll
remeasure (and rephotograph) later today.
Sorry about that.
John
----
John Ackermann N8UR said the following on 04/09/2006 11:14 AM:
> This morning I took 'scope shots of three 74AC04 gates paralleled
> through 47 ohm resistors, and of a single gate through a 47 ohm resistor.
>
> There's very little difference in rise time -- 2.5ns (10% to 90%, using
> the post-ringing high level as 100%) for three gates, and 2.35ns for a
> single gate. As expected, the output voltage using a single gate was
> significantly lower; the three-gate voltage was 3.56v p-p while the
> single-gate voltage was 2.32v p-p.
>
> The test setup was an HP 5363 time synthesizer set to generate a 1MHz,
> 50% duty cycle square wave through a 4 foot RG-58 cable driving a TADD-3
> board set for 50 ohm input termination. The TADD-3 output went through
> a 4 foot HP 50 ohm test cable (the ~RG-58 thickness, highly flexible,
> gray jacket type) into a Tek 2465B 400MHz scope with 50 ohm internal
> termination.
>
> John
>
>
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