[time-nuts] Frequency Dividers

Hal Murray hmurray at suespammers.org
Thu Aug 10 05:25:52 UTC 2006


> Or use 74193 synchronous counters. You will have only one gate per
> chip  worth of jitter. 

I think there should be only one gate of jitter per string of chips.  The 
whole chain is synchronous.  You have to wait for the carry to settle, then 
they all change on the same clock edge.

I'm assuming you are using something like the top bit of the counter for the 
PPS signal rather than the ripple carry output which may be glitchy anyway.

Of course, now you have a clock distribution problem.

Might be simpler to use a PIC or CPLD.  :)

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