[time-nuts] An example of phase noise

Brooke Clarke brooke at pacific.net
Sun Aug 20 19:44:22 UTC 2006


Hi John:

It's my understanding that the lowest jitter comes about when the 
highest output divisor is used.
In case of ties use the lowest VCO divisor.  See:
http://www.pacificsites.com/~brooke/BTSG.shtml

Have Fun,

Brooke Clarke

-- 
w/Java http://www.PRC68.com
w/o Java http://www.pacificsites.com/~brooke/PRC68COM.shtml
http://www.precisionclock.com



John Ackermann N8UR wrote:

>Poul-Henning Kamp said the following on 08/20/2006 02:37 PM:
>  
>
>>In message <44E89DD9.7090303 at febo.com>, John Ackermann N8UR writes:
>>
>>
>>    
>>
>>>Thought this might be interesting.  I took a spectrum analyzer shot of
>>>my ICS525 "Clock-Block" synthesizer at 250MHz, and overlaid it with a
>>>shot of an RF signal generator (Marconi 2202A) at the same frequency,
>>>and using the same reference source.
>>>
>>>The 2202A is designed for bench use and isn't noted for particularly
>>>good phase noise, but you can see the dramatic difference between the
>>>two units (the ICS525 is in red, the 2202A in cyan).
>>>
>>>That's why the Clock-Block isn't recommended for RF use!
>>>      
>>>
>>Have you played with the various PLL configurations that give the
>>same output frequency to see what difference they make ?
>>    
>>
>
>No, I haven't done that.  In this case, all three results from the
>calculator (lowest error, jitter, and current) used the same jumper
>settings, and I haven't messed with the formulas to come up with other
>possibilities.
>
>However, some other experiments indicate that the phase noise is better
>when only the "V" divisors are used; using the "R" and particularly "S"
>divisors results in quite a bit more noise.  If you look at the phase
>noise plots at http://www.febo.com/time-freq/hardware/ICS525/index.html
>you can see the difference between a simple divisor configuration and a
>more complex one.
>
>John
>
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>  
>



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