[time-nuts] GPS Timing prob

Tom Clark, K3IO K3IO at verizon.net
Wed Aug 23 17:37:09 UTC 2006


   [1]SAIDJACK at aol.com wrote:

   Hi Tom,



   yes, this clock granularity would be of interest. Do you have a more
   detailed description of how you guys implemented this?



   Also, how do you handle negative delays, e.g. the M12 is sending it's
   1PPS too late?



   thanks,
   Said

   The "negative delays" is pretty trivial. delay line has a delay of the
   form x+y*n; the "raw" 1PPS output is advanced by (x+y*n/2) so that the
   average in the middle of the delay range. The block diagram is pretty
   much as shown in the "Timing for VLBI (2005)" slide #26 with the
   results as in slide #29. The microprocessor is a PIC and Rick is the
   guru who wrote the PIC code to parse the sawtooth value and write it
   out to the Dallas Semi delay line chip. In his CNS Clock2, the
   circuitry is buried in the middle of a larger board.
   Tom

References

   1. mailto:SAIDJACK at aol.com



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