[time-nuts] Digital PLL ICs, alternatives and digital loop filters

[Tim Shoppa]

"Stephan Sandenbergh" <stephan at rrsg.ee.uct.ac.za> wrote:
> Another question for today - I have checked out some digital PLL ICs (more
> specifically the one's from AnalogDevices. It seems as if they've got some
> pretty neat stuff.) As I mentioned in my previous mail: I want to lock a
> GPSDOs 10MHz to a 100MHz OCXO using some sort of PLL.

OK here's where I get lost. I think you mean you want to lock the 100MHz
OCXO to a GPSDO's 10MHz output, which itself is necessarily locked to a
much lower frequency output from a GPS receiver.

> I find the PLL ICs
> convenient because they've got everything that is needed already built-in.
> Also, the phase detector and dividers are all optimised for low jitter. 

"Low jitter" is a very vague term. Depending on context it can vary
by at least a factor of 1000. The AD stuff is good, but it's
far from the best lab instruments. If the jitter in the GPS receiver
is in the few nanoseconds (not the best but typical of something
from the last decade) then it doesn't matter much if elsewhere in the
chain the jitter is held to picoseconds.

> Can anyone give me some pointers regarding this? If I need a low noise
> 100MHz output, is the digital PLL and a 100MHz OCXO a good choice? I guess
> that analog PLL techniques are better, but is it worth all that effort?

Analog PLL techniques are not necessarily better. Digital PLL's are
remarkable in their ability to produce corrections for slowly (modeled
by a linear or quadractic fit) tuned OCXO's. Try implementing an
analog value that must track linearly or quadractically to a part per
million over a few days and you might decide that digital really is
easier :-).

But to determine what's best you will probably have to come up with
some specs (phase noise?) for what you actually need.

Tim.