[time-nuts] GPS orthodontics: time averaging theory

[Brooke Clarke]

Hi Bruce:

Thanks for the link to meta stable references.  The referenced TI paper at:
http://www.klabs.org/richcontent/General_Application_Notes/mestablestates/meta_ti.pdf
in Fig 10 on pdf page 13 indicates that the meta state problem is solved 
by simply cascading a couple of D Flip-Flops.
I think this is also what's done in the HP paper on printed page number 
7 in Fig. 7 Synchronizing Circuit.

Have Fun,

Brooke Clarke

w/Java http://www.PRC68.com
w/o Java http://www.pacificsites.com/~brooke/PRC68COM.shtml
http://www.precisionclock.com



Dr Bruce Griffiths wrote:

>Brooks
>  
>
>>>>The "pitfalls" Dave mentions are:
>>>>
>>>>PARTIAL PULSE BIAS:  very narrow gated clock pulses are not counted,
>>>>thereby introducing a bias as computed in his eq(1).   Note that all 
>>>>the
>>>>parameters on the right side of eq(1) are constant, thus the bias is
>>>>constant.  A constant bias is important for a frequency counter or a 
>>>>TIC
>>>>since all measurements will be slightly off, but for phase locking it
>>>>makes no difference, it just moves the phase setpoint a tiny bit.  
>>>>Forget
>>>>the synchronizer.
>>>>
>>>>        
>>>>
>>>This analysis neglects the problem of metastable states. Whilst these
>>>cannot be eliminated a simple shift register synchroniser can be 
>>>employed
>>>to reduce the metastable state rate to less than once in the age of the
>>>universe or less if required.
>>>      
>>>
>>I don't see that metastable states are involved since the 4520 counter 
>>has
>>no setup time that would compete with the 24 Mhz clock. - the 4520 input
>>gate either passes a very narrow pulse or it doesn't.
>>
>>    
>>
>A common misconception is that a flipflop can only enter a metastable 
>state when the setup or hold times of the D (or J+K)  with respect to 
>the clock are violated.
>Perhaps the overwhelmingly common example of the possibility of 
>metastability when using a flipflop to synchronise asynchronous data to 
>a clock leads to this assumption.
>
>This assumption is incorrect, runt pulses applied to the clock input or 
>asynchronous inputs (set, reset etc) of a flipflop can also cause 
>metastability.
>Every bistable circuit has a metastable state and there are many ways of 
>attaining that metastable state.
>
>NASA and others believe this:
>http://www.klabs.org/richcontent/General_Application_Notes/mestablestates/MetastableStates.htm
>
>Bruce
>
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>