[time-nuts] Conditioning clock signal paths

[Poul-Henning Kamp]

In message <003f01c69a9d$62158bc0$401c9e89 at Stephan>, "Stephan Sandenbergh" writ
es:

>Now for the paradox: Do you filter your digital signal to lower the noise
>bandwidth? Or do you want a high as possible rise time (slew rate) to get
>the best PSSR?

The advantage to digital signals (ie: square-oid signals) as opposed
to analog signals (ie: sines) is that the slew-rate is higher.  That
means that it is less important at which precise voltage the
L->H or H->L transistion happens and therefore you don't need
precise analog reference voltages in your logic circuits.

The low slewrate of a sine would mean that even small changes
in threshold voltage would come out as large jitters in time.

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