[time-nuts] Some results of PRS10 and Trimble Resolution
SAIDJACK at aol.com
SAIDJACK at aol.com
Wed Jun 28 20:19:04 UTC 2006
Hi Stephan,
as CH said, the antenna delay is a "static" setting in the M12+, it's not
designed to be updated every second. I think it is only usefull in cancelling
out systemic delays in the setup such as TIA, delay-line, cabling etc.
Yes, we do run our sampler at 150MHz, with a resulting +-3.33ns resolution
uncertainty. I know of one company making Military GPSDO's, and they use 5MHz
sampling, so they have a 200ns window of uncertainty, seems to be enough for
their application.
Using an interpolator with a slow basic clock as Magnus suggests is probably
the easiest way to prevent EMI issues, but it has some disadvantages such as:
* You need to design a fairly tricky high-linearity charge pump to make it
work well, using high-quality components such as Polyester caps, low
INL/DNL/Tempco ADC's and ADC reference, or high quality comparators and
sample-and-holds, etc to make it insensitive to temperature changes etc. This is
essentially an analog design, with voltages being captured by an ADC, then converted to
time steps in software.
* The interpolator needs to be calibrated to give good results, especially
if the charge pump is not very linear. This is also needed due to temp
changes, as well as the ADC's errors such as the INL/DNL etc. This could be done
automatically, but does require a bit of circuitry and know how.
The advantage of the interpolator is that it can have a very high resolution
(ps) if designed properly. I have a Wavecrest interpolator board at home
that has 10ps resolution, and it is bigger than one of the old full-size AT IBM
motherboards... its tricky circuitry to design and make it work well. One
interesting fact is that Wavecrest uses actual rigid coax cables wound up in
loops to create delays on that board! They do suggest to calibrate the system
every 24 hours, or if there is a 5 Deg C change in temp.
Using the digital approach, you only need two parts: a fast PLD/FPGA, and an
external clock source (10MHz for example if the PLD has a PLL).
Depending on the PLD, you could get one that has an internal PLL running at
500MHz or even faster from your external 10MHz. These fast signals are only
inside the FPLD/FPGA, so it's easy to shield the circuit to prevent EMI.
NEC-Tokin makes ferrite shielding materials for exactly this purpose
(self-adhesive, you can glue them onto the PLD).
We have an option to place the entire PLD circuit inside a Faraday
metal-shield on our Fury GPSDO, no issue with EMI in that case.
bye,
Said
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