[time-nuts] Motorola Oncore GPS Interface Board

[Magnus Danielson]

From: Dr Bruce Griffiths <bruce.griffiths at xtra.co.nz>
Subject: Re: [time-nuts] Motorola Oncore GPS Interface Board
Date: Tue, 28 Nov 2006 14:36:19 +1300
Message-ID: <456B9293.5080107 at xtra.co.nz>

> Hal Murray wrote:
> >> Driving a full 5V TTL signal into a 50 ohm load is another matter -
> >> you  need a lot of DC power (1/2 watt) to do that. I was just using a
> >> Liner Tech LT1010 for a similar job - it would get the job done, but
> >> folks here might complain about the phase noise. 
> >>     
> >
> > Where does that phase noise come from and/or what should I do to minimize it 
> > if I need some sort of buffering?
> >
> > Is there a general rule about digital chips vs analog chips?
> >
> >   
> Phase noise is produced by the internal noise of the active devices 
> employed as well as the passive components such as resistors.
> Poor quality components like some capacitors can also generate 
> significant excess phase noise.
> In the final analysis everything is analog during switching transitions, 
> even digital chips.
> The jitter in the timing of a logic edge transition is determined by the 
> input signal jitter plus any noise on the finite risetime input as well 
> as internal noise in the logic circuit.
> Using the same chip to buffer other unrelated logic signals will produce 
> ground bounce that may affect the effective switching threshold for a 
> PPS signal should a transition of the unrelated logic signal occur too 
> close to a PPS transition. The inductance of the chips power and ground 
> connections along with the load on the unrelated signal buffer output 
> together with the PPS input signal risetme determines the significance 
> of this effect.

I.e. normal signal integrity issues. If you view every other signal as a
potential threat to your signal (including other signals which you want to
measure) you want to minimize the coupling as much as possible. Then it is more
an issue of "common sense". "common sense" involves a certain amount of
understandning thought, but looking at signal integrity issues is certainly
there. You can also make your signal less sensitive to interference. In one
case we added a small cap to let higher freq signals bypass downto ground and
that interference was effectively reduced.

> In a low phase noise oscillator using analog techniques is essential as 
> it is then possible to provide local negative feedback to suppress 1/f 
> noise generated by the active devices.

You can actually lower the phase noise by interlocking a 2 or more oscillators
in mutual synchronisation, which you then can steer through a common VC
contribution. The trick is to set the loop bandwidth(s) suitably.

> However even if you are forced to 
> use digital devices in an oscillator it is possible to significantly 
> reduce the phase noise if the principles outlined in the latest 
> extensions to Leeson's theory of oscillator phase noise are used.

I may have asked this before, but do you happend to have a few references on
the extensions to Leeson's theory?

Cheers,
Magnus