[time-nuts] How to measure Allan Deviation?

[Magnus Danielson]

From: Dr Bruce Griffiths <bruce.griffiths at xtra.co.nz>
Subject: Re: [time-nuts] How to measure Allan Deviation?
Date: Tue, 24 Oct 2006 12:35:43 +1300
Message-ID: <453D51CF.4030307 at xtra.co.nz>

> Magnus
> 
> The drawback with a CPLD is that most have a relatively high dc supply 
> current.

The good old XC9536 will draw 42.24 mA according to the formula given
(assuming the 24 macrocells needed for a divide by 10.000.000, running at
10 MHz and in high performance mode). This is a wooping 211,2 mW. Now, that is
even an overestimation since most MCs will have a static state except for the
clock. On the output side we don't have to drive anything but the PPS output,
saving us alot of power to pull parasitic caps we don't need to fiddle with.

I have a bunch of them lying around doing nothing good at the moment...

> I have a couple of CPLD designs that work the way you advocated.
> A CMOS divider has the attraction that its power supply current can be 
> relatively small even when the (small duty cycle) output drives a 50 ohm 
> load.

For most of my applications, I don't consider the heating of 100-200 mW a
major issue.

> The other problem with CPLDs is most are surface mount and use small pad 
> separations which can be problematic for home construction.

There are IC holders to solve that. Most of the pins doesn't have to be
driven, so there is plenty of room to solder in at the 2,54 mm spacing given.

> I have posted the pathological design to the list.

I missed that one.

> It is intended as a warning to be careful, even though one has these 
> nice slow low power supply noise parts in the drawer which can be used 
> to reliably generate a 1 PPS output, the divider will severely degrade 
> the measurement accuracy. It is even so pathological that one cannot 
> reliably resync the output to the input clock without resorting to 
> exceedingly expensive heroic measures such as a triple or quadruple 
> cascaded synchronisers (synchronising first to 100KHz output of 2nd 
> 4017, then to the 1MHz output of the first 4017 followed by  the 
> expensive synchroniser) The final set of synchronisers probably requires 
> a series of tapped delay lines that track the propagation delay of the 
> first divider, eventually the last synchroniser is clocked by the input 
> clock.

Indeed. But why fall back to such old technologies when newers may be used
with a little care? Not that there is something wrong with good old 4017s,
but they isn't really the speediest things that has come out of the factory
in the last decade or so.

Cheers,
Magnus