[time-nuts] Minimising effective divider propagation delay

Dr Bruce Griffiths bruce.griffiths at xtra.co.nz
Tue Sep 26 07:54:42 EDT 2006

Brian O'Connor <[1]vk4gtw at bigpond.com> wrote:
> I note that Shera's QST article refers to using the 1 MHz
> output from a HP5328A.  Is there any degradation of
> performance or increased thermal sensitivity due to the use
> of a HP marked 7490 (ripple counter) to divide down to 1 MHz?
> Would use of a synchronous divider or the TVB PIC approach
> yield a worthwhile improvement?

Don't forget the various ring-counter implementations, too.
Everybody unfortunately always focuses on the binary counters
(35 years ago it was true too! Look at all the hobbyist articles
in the 70's based around 7490's...)

TVB's PIC approach has a lot of leverage for high and funky division
ratios but for divide-by-10 there's the good old CD4017 (actually
a ring counter with decoded states) and faster modern versions like
the 74HC4017 et al. For the propogation delay minimization purist
I suppose the decoded states take away points, but for them there's
the 6-stage shift register DIP's.


   You can always follow your slow divider with a fast D flipflop to
   resynchronise the divided output to the input clock. A 74AC74 will
   reduce the clock to output transition delay to a few nanoseconds, a
   modern PECL or similar D flipflop will reduce this delay to a few
   hundred femtosec.


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