[time-nuts] Gate propagation delay jitter

Dr Bruce Griffiths bruce.griffiths at xtra.co.nz
Mon Apr 9 01:16:49 EDT 2007


The attached table of logic gate propagation delay jitter should prove 
somewhat challenging to verify with a time interval counter or similar 
device.
In fact devising any method of verifying these figures will be somewhat 
problematic.
However it could be done using by looking at the change in the output 
noise of a high resolution pipeline ADC when such a gate is switched 
into the sampling clock path.
Does anyone have any other practical method of measuring such small jitter?

Bruce
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