[time-nuts] Gate propagation delay jitter
Dr Bruce Griffiths
bruce.griffiths at xtra.co.nz
Mon Apr 9 02:11:01 EDT 2007
David Andersen wrote:
> Dr Bruce Griffiths wrote:
>> The attached table of logic gate propagation delay jitter should prove
>> somewhat challenging to verify with a time interval counter or similar
>> In fact devising any method of verifying these figures will be somewhat
>> However it could be done using by looking at the change in the output
>> noise of a high resolution pipeline ADC when such a gate is switched
>> into the sampling clock path.
>> Does anyone have any other practical method of measuring such small jitter?
> Depending on how much the environment affects the jitter, you could
> chain a bunch of them together and analyze the resulting distribution.
> You'd only see the tails of the distribution when the sum of the jitter
> exceeded your measurement threshold, but if you were willing to make
> some indepdence and gaussian assumptions, the analysis should be possible.
> (The sum of two gaussians has variance equal to the sum of the variance
> of the input gaussians, assuming the variables are independent. The
> thing I'd worry about is that the jitter you end up measuring is more
> affected by the environment - temp, EMI, etc. You could correct for
> that by then measuring the variance of 2x as many chained elements; if
> the variance was >2x, you'd know you have correlation.)
> But really, I'd wager there are some very nice, known statistical
> techniques for doing this. I'm just making something up that seems
> time-nuts mailing list
> time-nuts at febo.com
Yes, more intended for a challenge to see how long a chain is required
for a particular time interval counter to be able to achieve a
repeatability of say 10% in measuring the jitter. Also useful for design
purposes when one wants to have some idea of the limiting jitter of a
gate. Enclosing the test circuit in a massive aluminium block should
help with the thermal stability and with maintaining a low (external)
EMI environment, if one wishes to measure the low frequency jitter
If the jitter of your time interval counter is reasonably stable one can
measure rms jitter of around the same value with good accuracy (provided
the counter resolution is adequate). For counters limited by their
hardware resolution, measuring rms jitter down to about the resolution
limit should be feasible.
1) A 53132A jitter down to 150ps rms or so (equivalent to a chain of
4700 HCT gates)
2) A 5370A/B jitter down to 35ps rms or so (equivalent to a chain of 253
3) A Wavecrest device down to 3ps rms or so (equivalent to a chain of 2
Thus for making this sort of measurement with HCT gates it would appear
that the Wavecrest us the only timer counter that is practical to use
unless one has a lot of PCB real estate and devices available.
However if one were to build a ring oscillator with such a inverting
gate chain then it may just be easier to measure its phase noise floor.
This is a somewhat indirect technique, using a high speed ADC (with the
DUT switched into and out of the sampling clock path ) converting a low
noise 100MHz input signal seems simpler.
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