[time-nuts] Gate propagation delay jitter

Ulrich Bangert df6jb at ulrich-bangert.de
Tue Apr 10 05:40:35 EDT 2007


Bruce,

the following is part of a discussion in comp.arch.fpga:

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.
Hi, 
I would like to know what are the common methods of introducing 
delays as low as 10ps between two outputs in an FPGA. I do not 
currently have a specific FPGA in mind. I am just looking for a 
general answer. 

 I know there are DCMs but this usually adds jitter and one needs to 
wait for the DCM output to phase lock before the signal is stable and 
it might take too long in our case. Basically I would want to power up 
a board and have the delay be set in as short a time as possible. I 
also need to minimise jitter to a minimum so that the two signals are 
NEVER high at the same time. Thanks for any answer. 
Amish 
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Amish, 
The only method I am aware of is hand routing.  10ps is too small to 
really be able to hold to in all cases.  With 35ps p-p jitter (minimum) 
in any FPGA, and +/- 10 ps route matching (due to process variations 
chip to chip), this may be impossible. 
Austin (Leesa)
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Austin, 
> With 35ps p-p jitter (minimum) in any FPGA... 
I am currently designing some circuitry that needs to have jitter as low
as 
possible, therefore this spec is most interesting for me. Are you
talking 
about jitter introduced by DCMs or does ANY logic contained in an FPGA 
exhibit this jitter even when clocked with a low jitter clock. I have a
0.8 
ps RMS jitter clock source available (DS4077). If the logic that I would

like to clock with it would make a 35 ps pp minimum jitter out of it
this 
would be a sheer catastrophe for me! 
Best regards 
Ulrich Bangert 
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Ulrich, 
Just go into any CMOS chip, and then immediately leave that chip. 
That is 35 ps right there (a 74AHC04 for example). 
If you use LVDS, and have perfect terminations, maybe it becomes 25 ps. 
Call it a limitation of the technology of bulk CMOS. 
If you do anything else, the number just gets bigger. 
If you anything wrong, the number also gets bigger (bad bypassing, bad 
SI, etc.) 
Austin (Leesa)
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Austin Leesa's opinion is in heavy contrast to your table but he is a
very experienced man. So, whom to believe?

Best regards
Ulrich Bangert

> -----Ursprüngliche Nachricht-----
> Von: time-nuts-bounces at febo.com 
> [mailto:time-nuts-bounces at febo.com] Im Auftrag von Dr Bruce Griffiths
> Gesendet: Montag, 9. April 2007 07:17
> An: Discussion of precise time and frequency measurement
> Betreff: [time-nuts] Gate propagation delay jitter
> 
> 
> The attached table of logic gate propagation delay jitter 
> should prove 
> somewhat challenging to verify with a time interval counter 
> or similar 
> device.
> In fact devising any method of verifying these figures will 
> be somewhat 
> problematic.
> However it could be done using by looking at the change in the output 
> noise of a high resolution pipeline ADC when such a gate is switched 
> into the sampling clock path.
> Does anyone have any other practical method of measuring such 
> small jitter?
> 
> Bruce
> 





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